[SI-LIST] Re: Dielectric strength
- From: christopher.heard@xxxxxxxxxxxx
- To: esayre3@xxxxxxxx
- Date: Sun, 2 May 2004 21:16:05 -0400
Ed,
The answer depends on a whole lot of factors...
0) Usually power supplies provide isolation transformers which allows FR4
backplanes and plug-in cards to not be held to the same standards of
primary voltages. If you have this case, creepage and clearance values
from EN60950 are a function of the following things:
1) Level of Insulation. Are you providing protection from electric shock?
Functional, Basic or Reinforced will be the choices. Functional Insulation
distances are permitted by abnormal and HiPot testing. Basic or Reinforced
insulation is required for TNV2 voltages over 60V.
2) Pollution Degree. "2" is typical of IT equipment.
3) Working Voltage. 48V telco systems can see voltages near 70V. If an AC
power supply is providing the DC power, the max voltage may be different.
4) Material Group. "III" for FR4 typically due to the comparitive tracking
index value of 175.
Just like signal integrity, creepage and clearance isn't black and white.
I sometimes contact UL and VDE directly on most issues to make sure.
Companies like Curtis-Straus and NTS in Littleton Ma area are great places
to start to get a feel for these topics.
Chris
**********************
Chris Heard
Teradyne
Work: 603-879-1031
Cell: 508-277-5780
SMS Text Message: 5082775780@xxxxxxxxx
Email: christopher.heard@xxxxxxxxxxxx
Ed Sayre III
<esayre3@xxxxxxxx To: si-list@xxxxxxxxxxxxx
> cc:
Sent by: Subject: [SI-LIST] Dielectric
strength
si-list-bounce@fr
eelists.org
04/28/2004 10:40
AM
Please respond to
esayre3
Hello All,
I have few questions related to the creepage and clearance for any PCB
dielectric Although this is not a direct SI topic it does impact the
performance of a system by constraining the spacings, layer assignments and
layer count as well as many aspects that effect Signal
integrity. According to the spec IEC60950 (replacing UL1950), Section
6.1.2 requires up to 1.5kV isolation for telecommunication networks to
ground (or primary power). If FR4 is assumed, with a dielectric strength
roughly 1250kV/mil the calculation for the required thickness of FR4 is
clear. That is in the vertical direction of the PCB. My question is
directed at the lateral spacing for internal layers as well as external
layers. Since a PCB is laminated and not homogenous I would expect the
discharge path would along the interface boundary of the layers where the
dielectric strength is compromized. Is this a reasonable assumption? If
so, what is the dielectric strength of this interface and what should the
appropriate spacings be? Secondly for outer layers either covered with
solder mask or bare (in the case of a via) present a very different
problem. Again, I would expect the breakdown to occur along the interface
for solder mask to PCB dielectric or through the open air for the exposed
case.
What are peoples experiences and thoughts?
Regards
-Ed
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
NORTH EAST SYSTEMS ASSOCIATES, INC
-------------------------------------
"High Performance Engineering & Design"
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Dr. Edward Sayre 3rd e-mail: esayre3@xxxxxxxx
NESA, Inc. http://www.nesa.com/
5 Lan Drive, Suite 200 Tel +1.978.392-8787 x 218
Westford, MA 01886 USA Fax +1.978.392-8686
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