[SI-LIST] Re: Determination RLC value of a pin
- From: Ray Anderson <ray.anderson@xxxxxxxxxx>
- To: "maxsidhu@xxxxxxxxx" <maxsidhu@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 12 Dec 2012 17:44:06 +0000
Siddharth-
Typically when the RLC values for the various nets in a package are extracted,
the extraction accounts for the RLC parasitics from the top of the die bump to
the bottom of the BGA ball (for a flip-chip package). So even though pins (die
bumps) may have identical geometries for each net, the connecting traces in the
package may be of differing lengths which will lead to differing RLC values as
reported in the IBIS model.
Regards,
-Ray
Raymond Anderson
Senior Signal Integrity Staff Engineer
Programmable Platforms Development
Silicon Technology Group
Signal Integrity and Package Development Department
Xilinx Inc.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Siddharth Rajagopalan
Sent: Tuesday, December 11, 2012 8:22 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Determination RLC value of a pin
Dear experts,
I came across some IBIS files for DDR memory where there are
several RLC values for the pins of the same group. For example, Different pins
of DQ group have different RLC values. I was of the understanding that the
geometry of a pin (in this case, a bump under the
IC) determines the RLC value of that particular pin. Don't these pins have the
same bump geometry. why do we have different values?? Kindly help me correct my
understanding.
--
Thanks,
Siddharth Rajagopalan
Cisco systems
.
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