Hi all:
Thanks for all assistance.
I have another question,why the derating for tds/tdh increase when skew
rate of dqs gets lower?
I am simulating DQ/DQS timing of DDR3, in addition to ISI ,crosstalk,PI, Is
there other factors that I have to think about ? I measured the tDS/tDH by
the waveform of simulation,then compared with (tbase+skew rate derating) .
I am finding a simpler method now ,or could experienced people give me some
suggestions?
thanks
Mo Han
2015-04-14 4:37 GMT+08:00 Moran, Brian P <brian.p.moran@xxxxxxxxx>:
Mo-han
The derating tables are a composite of two functions. Baseline derating
is a function which increases
as slew rate decreases. This derating is only positive at slew rates of
less than 1V/ns, and is zero
everywhere else. The second function is calculated from a normalization
formula which
normalizes the setup and hold specs at the AC/DC threshold, for slew rates
other than 1V/ns,
which is the default used in establishing the setup and hold specs. In
this case higher slew rate
results in larger derating. When you combine the two functions you get a
composite curve which
is always zero at 1V/ns, and can be somewhat irregular below 1V/ns, but
above 1V/ns it always
increases with slew rate. Granted it does seem non-intuitive to penalize
margins due to higher slew
rates, but this is the technically correct result of the derating theory.
To some degree it does
relate to charge accumulation effects, as someone state earlier, but the
actual formula is
a simple equation. I forwarded a power-point document which explains
derating in more detail.
Brian Moran
Intel Corporation
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Hermann Ruckerbauer
Sent: Monday, April 13, 2015 12:25 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Derating values for DDR3-800/1066/1333/1600 tDS/tDH
Hello,
Yes, it sounds strange that setup/hold times are getting smaller with
slower slew rates and it is somehow difficult to describe this by e-mail
I'm just doing the Black Box of Memory Seminar (what is the reason for the
big Latency I have on answering this question ;-), and setup/hold times
with derating is 1 hour of explanation with quite some help of power point
animations.
So here the short version (which is for free ;-) ):
Setup/Hold times are defined at AC/DC level. If you have slower slew rates
the setuptime based on VREF and the engergy provided to the receiver for
switching is increased.
So AC/DC based you need less setup time for slower slew rate in order to
provide the same amount of energy to the receiver to ensure it is switching.
It would be great if this short paragraph could replace 1 hour of
talking, as I can use this time for other topics ;-)
Hermann
Our next Events:
Seminar "Open the Black Box of Memory"
(13.-14.04.2015 and 15.-16.04.2015) in Stockholm Sweden
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
Tel.: +49 (0)991 / 29 69 29 05
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
Am 13.04.2015 um 17:16 schrieb Paul Callahan:
Is there any better reference than the February 2010 SI-LIST discussionsby: Brian Moran, Hermann Ruckerbauer, Perry Qu, el. Al.?
Paul Callahan------------------------------------------------------------------
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Boris Bakshan
Sent: Monday, April 13, 2015 3:38 AM
To: hanmoggq@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Derating values for DDR3-800/1066/1333/1600
tDS/tDH
Hello Mo han,
With faster edges, larger timing budget is imperative. Think of it
this
way: If the edges are slow enough, there would be enough charge
accumulating at the gates of receivers to trigger the receiving stage.
If you make it faster, it should be comprehended with larger setup
times to allow enough charge accumulation.
This might help:
[image: Inline image 1]
On Mon, Apr 13, 2015 at 9:42 AM, mo han <hanmoggq@xxxxxxxxx> wrote:
HI experts:
why dose the dq slew rate increase,the tDS and tDH increases at the
same time?
Best Regards!
Peter
[image: å åµå¾ç 1]
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