[SI-LIST] Re: Derating values for DDR3-800/1066/1333/1600 tDS/tDH

  • From: Boris Bakshan <bbakshan@xxxxxxxxx>
  • To: hanmoggq@xxxxxxxxx, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 13 Apr 2015 11:38:05 +0300

Hello Mo han,
With faster edges, larger timing budget is imperative. Think of it this
way: If the edges are slow enough, there would be enough charge
accumulating at the gates of receivers to trigger the receiving stage. If
you make it faster, it should be comprehended with larger setup times to
allow enough charge accumulation.
This might help:

[image: Inline image 1]

On Mon, Apr 13, 2015 at 9:42 AM, mo han <hanmoggq@xxxxxxxxx> wrote:

HI experts:
why dose the dq slew rate increase,the tDS and tDH increases at the same
time?
Best Regards!
Peter
[image: 内嵌图片 1]


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