[SI-LIST] Re: Definition of spreading inductance
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Charles.Grasso@xxxxxxxxxxxx
- Date: Mon, 23 May 2005 13:38:52 -0400
Charles,
Spreading inductance is just the inductance from point A to point B,
when the connecting vehicle is a plane or a set of planes. You can find
calculations for a specific FPGA power/ground arrangement in papers and
slides on our site:
at: http://www.teraspeed.com/publications.html
*/NEW/ - High Performance FPGA Bypass Networks *
*/NEW/ - Capacitor Placement
*
*
*
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Grasso, Charles wrote:
>Hi - Can anyone point me to a concise defensible
>definition of "spreading inductance"?
>
>Thanks!
>
>Best Regards
>Charles Grasso
>Senior Compliance Engineer
>Echostar Communications Corp.
>Tel: 303-706-5467
>Fax: 303-799-6222
>Cell: 303-204-2974
>Pager/Short Message: 3032042974@xxxxxxxx
>Email: charles.grasso@xxxxxxxxxxxx;
>Email Alternate: chasgrasso@xxxxxxxx
>
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>Behalf Of sunil bharadwaz
>Sent: Monday, May 23, 2005 10:32 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: 10-Layer Stack up
>
>
>Thomas ::
>
>Thanks for that input.
>
>Best Regards
>Sunil
>--- Thomas McGonigle <temcgonigle@xxxxxxxxx> wrote:
>
>
>
>>Sunil,
>>
>>You might want to put the power and ground planes
>>next to each other, making a
>>"sandwich". This created an embedded bypass
>>capacitor, and also lowers the
>>spreading inductance of the planes, both of which
>>reduce switching noise at
>>high frequencies. See the Xilinx Virtex-4 PCB
>>Designer's guide, pages 35 to
>>37. You can find it at :
>>http://www.xilinx.com/bvdocs/userguides/ug072.pdf
>>
>>
>>--- steve weir <weirsi@xxxxxxxxxx> wrote:
>>
>>
>>>Sunil, see any of the previous comments about
>>>
>>>
>>managing cavities.
>>
>>
>>>Steve.
>>>At 08:09 PM 5/22/2005 -0700, sunil bharadwaz
>>>
>>>
>>wrote:
>>
>>
>>>>Hi All ,
>>>>We are trying to design a board with FPGA's.
>>>>We are having two Virtex-4 devices on the
>>>>
>>>>
>>board.The
>>
>>
>>>>max intended speed will be 130 Mhz.This is a ten
>>>>layer,50 ohms controlled impedance board.
>>>>The high speed signals have been routed in the
>>>>
>>>>
>>Layers
>>
>>
>>>>3,4,7,8.
>>>>We have come up with a stack up as follows.
>>>>I have also attached the stack up details as a
>>>>
>>>>
>>word
>>
>>
>>>>doc.
>>>>
>>>>I'am looking for some
>>>>improvements/concerns/suggestions on the Shown
>>>>
>>>>
>>stack
>>
>>
>>>>up.Any feed back would be highly appreciated.
>>>>
>>>> Thanks in advance
>>>>
>>>> Best Regards
>>>> Sunil
>>>>
>>>>
>>>>0.0325 Copper plating layer 1 5.468 mil trace
>>>>
>>>>
>>width 50
>>
>>
>>>>ohms single ended
>>>>0.0175 Copper foil layer 1
>>>>0.0940 Prepreg 1-2
>>>>0.0350 Copper foil layer 2 plane ---GND
>>>>0.1524 Core 2-3
>>>>0.0350 Copper foil layer 3 6.278 mil trace
>>>>
>>>>
>>width 50
>>
>>
>>>>ohms single ended
>>>>0.1194 Prepreg 3-4
>>>>0.0350 Copper foil layer 4 6.278 mil trace
>>>>
>>>>
>>width 50
>>
>>
>>>>ohms single ended
>>>>0.1524 Core 4-5-6
>>>>0.0350 Copper foil layer 5 plane---Power
>>>>
>>>>
>>Plane (3.3
>>
>>
>>>>Volts I/O)
>>>>0.2032 Prepreg 5-6
>>>>0.0350 Copper foil layer 6 plane----GND
>>>>0.1524 Core 6-7
>>>>0.0350 Copper foil layer 7 6.278 mil trace
>>>>
>>>>
>>width 50
>>
>>
>>>>ohms single ended .
>>>>0.1194 Prepreg 7-8
>>>>0.0350 Copper foil layer 8 6.278 mil trace
>>>>
>>>>
>>width 50
>>
>>
>>>>ohms single ended
>>>>0.1524 Core 8-9
>>>>0.0350 Copper foil layer 9 plane-------
>>>>
>>>>
>>Power Plane
>>
>>
>>>>(2.5 Volts split plane )
>>>>0.0940 Prepreg 9-10
>>>>0.0175 Copper foil layer 10
>>>>0.0325 Copper plating layer 10 5.468 mil trace
>>>>
>>>>
>>width
>>
>>
>>>>50 ohms single ended
>>>>1.6195 Total PCB thickness in mm
>>>>
>>>>
>>>>
>>>>Yahoo! Mail
>>>>Stay connected, organized, and protected. Take
>>>>
>>>>
>>the tour:
>>
>>
>>>>http://tour.mail.yahoo.com/mailtour.html
>>>>
>>>>
>>>>-- Binary/unsupported file stripped by Ecartis --
>>>>-- Type: application/msword
>>>>-- File: stack1.doc
>>>>-- Desc: 354396701-stack1.doc
>>>>
>>>>
>>>>
>>>>
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>>8305 48 th Avenue
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>>tmcgonigle@xxxxxxxx
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