[SI-LIST] Re: Decoupling in DDR3 Applications
- From: "Marc Humphreys" <mhumphreys@xxxxxxxxxxxxxxxxxxx>
- To: "Hirshtal Itzhak" <ihirshtal@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 18 Feb 2010 08:52:33 -0800
Hirshtal,
I went though the brain scratching excersise a few weeks back. My
conclusion is it is really design dependent.
If you take a look at the allegro brd files for the various JEDEC raw cards
in some cases the ADD/CMD lines are routed over the VDD plane, simply for
efficent use of the available layers. DDR3 daisy chain toplogogy allows the
ADD/CMD to be routed in a very simple and clean fashion and on the same
layers as the data, but to keep the overall layer count down it makes sense
to route VDD and VSS on the same layers also but in doing so they ended up
routing the ADD/CMD signals over the VSS portion, and hense VTT is best
decoupled to VDD. You're then adviced to reference the ADD/CMD signal to
VSS on you board, which can be tricky depending on CPU pinout. If can't be
done at least place a fair sufficent decoupling at the DIMM socket in the
vicinity of the ADD/CMD signal pins. If this is an Intel based design take
a look at their the board layout for one of their CRBs that utilizes
unbuffered DDR3 dimms.
For an embedded design with enough layers to reference all your DDR signals
to VSS then it makes sense to decouple VTT and REFCA to VSS also.
Marc
----------------------------------------
From: "Hirshtal Itzhak" <ihirshtal@xxxxxxxxxx>
Sent: Thursday, February 18, 2010 7:59 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Decoupling in DDR3 Applications
Hello Experts!
I found out that the Unbuffered DIMM Design Specification 21C Page
4.20.19-30 (Revision 1.01 Nov 2009) recommends to decouple VTT by
decoupling capacitors to VDD. VREFCA has the same recommendation.
On the other hand, on the same page, VREFDQ is recommended to be
decoupled to VSS.
Also, I couldn't find any specific recommendation for the decoupling
voltage in the Unbuffered SO-DIMM Reference Design Specification 21C
Page 4.20.18-28 (Revision 1.0 Feb 2009).
Does anyone happen to know why decoupling is recommended to be done to
VDD rather than VSS in all cases? It seemed to me that VSS was always
the preferred voltage to decouple to. And if there's a good reason for
not doing it, then why the differences between the various voltages and
the two DIMM specs?
Also, is there a difference in regard to embedded (non-DIMM)
applications?
Thanks
Itzhak Hirshtal
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