[SI-LIST] Re: Decoupling capacitors

  • From: "Knighten, Jim L" <JK100005@xxxxxxxxxxxxxxxxxxxxxxxxxxx>
  • To: Larry.Smith@xxxxxxx
  • Date: Thu, 6 Jun 2002 13:04:07 -0400

Larry,

When you make these S21 measurements, is your board populated with ICs and
is it powered or un-powered?

Jim


Jim Knighten, Ph.D.
Teradata, a Division of NCR             http://www.ncr.com
17095 Via Del Campo
San Diego, CA 92127
USA
Tel: 858-485-2537
Fax: 858-485-3788
jim.knighten@xxxxxxx

 -----Original Message-----
From:   Larry Smith [mailto:Larry.Smith@xxxxxxx] 
Sent:   Thursday, June 06, 2002 9:30 AM
To:     Larry.Smith@xxxxxxx; mibrown@xxxxxx; ctwardy@xxxxxxxxxxxxxxxxxx
Cc:     si-list@xxxxxxxxxxxxx
Subject:        [SI-LIST] Re: Decoupling capacitors


Craig - You are asking some very good questions concerning verification
of PDS (power distribution system) design in manufacturing.

First of all, how does an SI group determine that a decoupling design
works?  Here at Sun, we use S21 measurements from a VNA to verify that
the measured impedance vs frequency on the PDS matches our
simulations.  But probing around with a frequency domain instrument is
outside of the comfort zone of most manufacturers.  If a big valued
capacitor is missing, you can tell pretty easily from the frequency
scan.  But if one out of 10 small valued capacitors are missing, you
will not detect it.  If a wrong part-number reel of capacitors is used,
it is possible to detect an impedance peak where there should not have
been one and an impedance dip at some other frequency.  These are the
best verification methods, but not likely to be implemented in typical
manufacturing lines.

ESR is an interesting issue.  Several years ago, when Silver Palladium
metallurgy was use in ceramic caps, we would see a 400% variation of
ESR across several vendors and perhaps a 200% variation from a single
lot from a single vendor.  As the industry has moved to Nickel and Base
metallurgy for X7R caps, the ESR's have dropped in half of what they
used to be.  I know I will get some disagreement on this, but I think
the ESR's are just about right.  The X7R/X5R capacitors have a Q of
about 2.  Three cap values per decade works well.  If the Q's were up
around 5 (as they are for COG/NPO caps), we would have to use 6 values
per decade to really flatten out the impedance vs frequency curve.
With the new metallurgy, we find that most cap vendors are within about
20% of each other for ESR.  That is close enough, certainly a lot
better than 400%.  All of our measurements and simulations are reported
on a log scale and typically displayed over 3 decades.  Impedance has to
double before it really stands out.

There are no specifications on ceramic capacitor ESR and no guarantees
that metallurgy won't change again.  We are on a bit of a crusade to get
cap vendors to publish typical ESR data for each capacitor P/N used for
decoupling.  That is not a min/max guarantee, but it will keep the ESR
values from jumping around like they have in the past.  Once they are
on-record with an ESR, and fully understand how important this is for
their customers, it will be harder to change it.  Placing a spec on ESR
implies testing and a cost adder for the caps.  I don't think any of us
want that.

Your perceptions are right on the money.  Maybe someday we will have
the equivalent of IBIS data for capacitors.  But the PDS CAD industry
is still in it's infancy.  People are just beginning to realize that
you can optimize the design of a PDS and are recognizing the importance
of doing so as the capacitors begin to take over all available
real-estate on our product boards.  And as we get more sophisticated in
design of the PDS, we will also have to get more sophisticated in the
verification of the PDS and batch control for our parts.

regards,
Larry Smith
Sun Microsystems

> From: "Craig Twardy" <ctwardy@xxxxxxxxxxxxxxxxxx>
> To: Larry.Smith@xxxxxxx, mibrown@xxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: Decoupling capacitors
> Date: Thu, 6 Jun 2002 09:47:55 -0400 
> MIME-Version: 1.0
> 
> Hi Larry;
> 
> How does manufactoring verify the  decoupling design works
> on the production PCBs?
> 
> I foresee two issues
> 
> 1. the right capacitors are not always installed.
>        
> 2. the design objectives are determined by ESR.
>       seems that the ESR of capacitors is a typically value.
>       it is not specified or guaranteed( ie measured).
>       a deviant batch of capacitors could cause havoc.
>         
>       is this perception correct?
> 
> 
> Are there other concerns?
> 
> suggestions?
> 
> Craig
> 
> 
> 
> -----Original Message-----
> From: Larry Smith [mailto:Larry.Smith@xxxxxxx]
> Sent: June 4, 2002 7:58 PM
> To: Larry.Smith@xxxxxxx; mibrown@xxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Decoupling capacitors
> 
> 
> 
> Mike - For SI purposes, there is not much you can do at the PCB level
> to help the PDS impedance above the package corner frequency.  However,
> there may (probably will) be EMI reasons to use capacitors on the core
> power planes to knock down emissions at higher frequencies.
> 
> We use 3 capacitors per decade to make the PDS impedance sufficiently
> flat.  The fifteen values of ceramic X5R/X7R capacitors that we most
> commonly use are:
> 
>       100uF   47uF    22uF
>        10uF   4.7uF   2.2uF
>         1uF   470nF   220nF
>       100nF   47nF    22nF
>        10nF   4.7nF   2.2nF
> 
> This menu is usually sufficient for SI caps.  We mount these caps on
> pads that are much less than 1nH so the series resonant frequencies
> (SRF) range from 360kHz to 150 MHz.  Five decades of capacitance value
> covers about 2.5 decades of frequecy because the SRF goes as the square
> root of capacitance.  The ESR's range from 2 mOhms to 300 mOhms, with
> the lower valued caps having the highest ESR.  1uF and below is
> available in 0603 case sizes.  100uF caps are now available in 1812
> size.
> 
> Our power planes generally have more than 10 nF capacitance.  The ESR
> of the capacitors below 10nF is so high that many, many capacitors are
> required in parallel to reach target impedance.  It is best to use
> power plane capacitance above about 100 MHz rather than try to do it
> with discretes.  There may be a few well defined EMI frequencies that
> you want to attack with carefully chosen high quality capacitors, but
> that is a different issue.
> 
> regards,
> Larry Smith
> Sun Microsystems 
> 
> > From: "Brown, Mike (AUS)" <mibrown@xxxxxx>
> > To: <Larry.Smith@xxxxxxx>
> > Cc: <si-list@xxxxxxxxxxxxx>
> > <snip>
> > 
> > range.  Individual capacitors have an impedance vs frequency profile
> > that look like a "V".  By selecting the optimum number of capacitors
> > with different values, it is possible to combine a lot of these "V's"
> > together to approach a flat curve over a broad frequency range.  That
> > essentially presents a resistance to the load over the frequency
> > range.
> > 
> > <snip>
> > = = = = =
> > Larry,
> > 
> > It would appear that I don't have to worry about board impedance above
the
> > package corner frequency, where the package X exceeds the target
> impedance.
> > I may need a bunch of different cap values and resonances to keep the
> board
> > and PDS impedance flat up to that frequency, however.
> > 
> > What is an acceptable spacing between the series-resonant "V's" to avoid
> > unacceptably high parallel resonance impedance peaks?  1 per decade?  1
> per
> > octave?
> > 
> > I know, I know.  "It Depends."  On what?
> > 
> > 
> > Thanks
> > 
> > Mike
> > 
> 
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