[SI-LIST] Re: Decoupling at 800Mhz

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: Aravind Sandeep <aravind.sandeep@xxxxxxxxx>
  • Date: Thu, 22 May 2008 22:31:01 -0700

In most PCB PDNs with 5mil or thinner dielectric, 800MHz is getting to 
be about beyond the point that the cavity dominates over the bypass 
capacitors with most decoupling schemes. You need to include analysis of 
your interconnect.

Steve

Aravind Sandeep wrote:
> Hi Subramanian,
> At high frequency the conventional decoupling capacitor looks like Besides
> the pure capacitance there is an Equivalent Series Inductance ESL and an
> Equivalent Series Resistance ESR.Capacitor shows capacitive behaviour in the
> lower frequency range; for frequencies higher than the series resonant
> frequency the behaviour becomes inductive. Optimum decoupling effect is
> found at series resonant frequency. This information should be available in
> capacitor data sheets. Although this information is given in the capacitor
> data sheet i would recommend to use a simulations before you proceed for
> prototyping.
>
> Thanks and Regards,
> Aravind
>
>
>
> On 5/22/08, Subramanian R <subramanian1683@xxxxxxxxx> wrote:
>   
>> Hi All,
>> We are planning to use a processor running at 800 MHz.
>> I was just reading up on the decoupling methods.
>>
>> The Processor PCB guidelines recommend using 1uF 0402 pack for high
>> frequency decoupling. But at 800 MHz, will not the cap/package inductance
>> dominate.
>>
>> The guideline doesn't say anything about plane decoupling also.
>>
>> Am I missing something? What are the best approaches for decoupling?
>>
>> Any suggestions will be very useful.
>>
>> Thank you in advance,
>>
>> Regards
>> Mani
>>
>>
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