[SI-LIST] Decoupling Capacitor
- From: "Nagaraj" <nagaraj@xxxxxxxxxxxxxxxxxxxx>
- To: "[SI-LIST]" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 13 Aug 2002 18:04:53 +0800
Hi SI Gurus,
Currently I am designing High Speed digital Board Using New Texas DSP
TMS320c64X series.
No of Power Pins sharing 1.4Volts and 3.3v are 71 & 51
Its Recommended to Have Decap for Each pin but its Practically impossible to
Provide that much
Can Anybody Advise me How many Decaps are Required?
We have separate Plane for both 1.4 and 3.3Volts.
(Stack up10+)
nagaraj
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Tadashi Arai
Sent: Tuesday, August 13, 2002 1:51 PM
To: [SI-LIST]
Subject: [SI-LIST] Re: planer capacitors
Hi Bill,
The reason is that there is almost no inductance with planer caps,
besides the discrete may have large. As you know, discrete caps behave
inductor rather than capacitor @ high frequency, so that impedance curve
is shown as "V" shape. You can only get effect at the bottom of "V".
Regards,
On Fri, 9 Aug 2002 10:38:57 -0700
"Bill Mueller" <williamm@xxxxxxx> wrote:
> Hello All,
>
> I've been doing digital design guides for a little over a year now,
> and was interested in a little more explanation on why planer
> capacitors are more effective at higher frequencies than discrete
> caps.
>
> Also, if you have a fairly large stack up (10+ layers) with several
> possible planer caps are there any additional considerations to be
> made?
>
> Thanks,
> Bill
>
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//// /// // / / / / / / / / / /
Tadashi Arai//Platform Developing Dept.,Desktop Prd Div. Fujitsu Limited
arap@xxxxxxxxxxxxxx TEL:+81-42-370-7624 Inagi-shi, Tokyo, Japan
/ / / / / / / / / / / // ///
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