Dear Members,
On behalf of the organizing committee, we would like to bring to your
attention that the paper submission deadline for the IEEE Electrical
Design of Advanced Packaging and Systems (EDAPS) Symposium 2016 has been
extended to September 12, 2016.
In addition, authors of accepted papers will be invited to submit an
extended version of their manuscript for a Special Section based on
EDAPS-2016 to be published in the IEEE Transactions on components,
packaging and manufacturing technology (T-CPMT).
The online paper submission will be available at the conference website
(http://www.edaps2016.org) until the extended deadline.
Please visit the website and find the updated deadline and the paper
submission process.
The IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)
Symposium is the premier international conference in the Asia Pacific
region to share the recent progress in modeling, simulation and
measurement for electrical design issues on chip, package, and system
levels. The EDAPS symposium consists of paper presentations, industry
exhibitions, workshops, and tutorials.
The EDAPS 2016 will be held at the Sheraton-Waikiki, Honolulu, Hawaii,
USA from December 14 to 16, 2016. The technical program of the symposium
not only addresses current technical issues but also brings out challenges
in IC designs, SiP/SoP packaging, EMI/EMC, EDA tools, and advanced 3D-IC
and TSV designs. As in the previous editions over a decade, EDAPS 2016
will provide a major platform for researchers from academia and industry
to exchange their knowledge and to build up networks.
We would like to cordially invite you to participate in the IEEE
Electrical Design of Advanced Packaging and Systems (EDAPS) 2016. The
online paper submission site is opened at the conference web site and
prospective authors are invited to submit papers.
[Conference Webpage]
http://www.edaps2016.org
[Important dates]
Extended Deadline for Regular Paper Submission : September 12, 2016
Acceptance Notification : September 21, 2016
Conference Date: December 14-16, 2016
[Venue]
Sheraton-Waikiki, Honolulu, Hawaii, USA
[Technical areas]
The technical areas of the conference are:
1. 3D-ICs/TSVs/Interposers
2. Testing on 3D-IC and SiP
3. Signal and Thermal Integrity
4. Power Integrity/Power Distribution Networks (PDNs)/Ground Noise
5. Multi-physics Simulation Techniques for SI/PI/TI Analysis
6. Design and Modeling for High-speed Channels and Interconnects
7. Time / Frequency Domain Measurement Techniques
8. Electronic Packages, SiP/SoP
9. IC and Package Level EMC
10. RF/mm-wave Packages
11. Embedded Passives
12. Power Electronic Packages
13. Advanced Simulation Tools and CAD
14. Substrate Technology for Packages and PCBs
15. Package Reliability
16. Others
For further information, please contact: admin@xxxxxxxxxxxxx
We look forward to seeing you in Hawaii in December 2016
Sincerely,
Jose Schutt-Aine
Madhavan Swaminathan
EDAPS 2016 Conference co-Chairs
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