[SI-LIST] Re: Damped voltage oscillation
- From: "istvan novak" <istvan.novak@xxxxxxxxxxxxxxxx>
- To: <ueda@xxxxxxxxxxxx>, "silists" <si-list@xxxxxxxxxxxxx>
- Date: Sun, 22 Jun 2003 20:19:36 -0400
Hi,
There were many publications on the subject. Here are a few:
- Gang Ji, Tawfik Arabi, Greg Taylor, Mark Beiley, "A Design Methodology for
The I/O Power Supply of Next Generation Packaging," Proceedings of EPEP2002,
October 21-23, 2002, Monterey, CA, pp.253-256
- Om P. Mandhana, "Analysis and Design of Critically Damped Power
Distribution Network for High Performance Microprocessor Systems,"
Proceedings of EPEP2002, October 21-23, 2002, Monterey, CA, pp.183-186
- St.Cyr, Novak, Biunno, Howard, "ARIES: Using Annular-Ring Embedded
Resistors to Set Capacitor ESR in Power Distribution Networks", EPEP2001,
Cambridge, MA, October 2001
- Shohei Fujio, Hideki Kabayama, Akihisa Sakurai, "Analysis on the Power /
Ground Plane Resonance Damping and Radiated Field Reduction with the RC
Termination" Proceedings of the 2001 IEEE EMC Symposium, August 13-17, 2001,
Montreal, Canada
- A. Waizman and Chee-Yee Chung, "Package Capacitors Impact on
Microprocessor Maximum Operating Frequency," Proceedings of the 51st
Electronic Components and Technology Conference, May 29 - june 1, 2001,
Orlando, FL
- Novak, "Reducing Simultaneous Switching Noise and EMI on Ground/Power
Planes by Dissipative Edge Termination," IEEE Transactions on Advanced
Packaging, August 1999, Volume 22, Number 03, p.274
Items 3 and 6 are available online. Let me know if you need the pointer, or
if you need more details on them.
Regards,
Istvan Novak
SUN Microsystems
----- Original Message -----
From: <ueda@xxxxxxxxxxxx>
To: "silists" <si-list@xxxxxxxxxxxxx>; "istvan novak"
<istvan.novak@xxxxxxxxxxxxxxxx>
Sent: Saturday, June 21, 2003 8:19 PM
Subject: Re: [SI-LIST] Damped voltage oscillation
> Hi, Istvan Novak and all
>
> Thanks you for your response.
> The meaning is the absorption of switching noise at high speed degital
> device.
> If it is really so, literature is being looked for.
> I want to know how there is effect by such a connection.
>
> Best Regards,
>
> Chihiro Ueda
> AET japan ,INC.
>
> ----- Original Message -----
> From: "istvan novak" <istvan.novak@xxxxxxxxxxxxxxxx>
> To: <ueda@xxxxxxxxxxxx>; "silists" <si-list@xxxxxxxxxxxxx>
> Sent: Sunday, June 22, 2003 6:33 AM
> Subject: Re: [SI-LIST] Damped voltage oscillation
>
>
> > Hi,
> >
> > Do you mean a design when resistanbce is added
> > in series to bypass capacitors to dampen resonance peaking?
> >
> > Regards,
> >
> > Istvan Novak
> > SUN Microsystems
> >
> > ----- Original Message -----
> > From: <ueda@xxxxxxxxxxxx>
> > To: "silists" <si-list@xxxxxxxxxxxxx>
> > Sent: Saturday, June 21, 2003 4:39 PM
> > Subject: [SI-LIST] Damped voltage oscillation
> >
> >
> > > Hi, ALL
> > > Does anyone know the example which damped voltage oscillation?
> > > The resistor is connected with the series in decoupling capacitor to
> > insert
> > > between power(vdd) and ground (gnd).
> > > Don't you know the paper, the materials?
> > > Chihiro Ueda
> > > AET japan INC
> > >
> > >
> > > *************************
> > > Engineering Division
> > > Chihiro Ueda
> > > AET JAPAN, INC.
> > > URSIS Bldg. 9th Floor
> > > 1-2-3 Manpukuji, Asaoku,
> > > Kawasaki-City,215-0004Japan
> > > TEL:81-044-966-9981
> > > FAX:81-044-951-1572
> > > mailto:ueda@xxxxxxxxxxxx
> > > http://www.aetjapan.com
> > > *************************
> > >
> > >
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