[SI-LIST] Re: Damped voltage oscillation
- From: <ueda@xxxxxxxxxxxx>
- To: "silists" <si-list@xxxxxxxxxxxxx>,"istvan novak" <istvan.novak@xxxxxxxxxxxxxxxx>
- Date: Sun, 22 Jun 2003 09:19:37 +0900
Hi, Istvan Novak and all
Thanks you for your response.
The meaning is the absorption of switching noise at high speed degital
device.
If it is really so, literature is being looked for.
I want to know how there is effect by such a connection.
Best Regards,
Chihiro Ueda
AET japan ,INC.
----- Original Message -----
From: "istvan novak" <istvan.novak@xxxxxxxxxxxxxxxx>
To: <ueda@xxxxxxxxxxxx>; "silists" <si-list@xxxxxxxxxxxxx>
Sent: Sunday, June 22, 2003 6:33 AM
Subject: Re: [SI-LIST] Damped voltage oscillation
> Hi,
>
> Do you mean a design when resistanbce is added
> in series to bypass capacitors to dampen resonance peaking?
>
> Regards,
>
> Istvan Novak
> SUN Microsystems
>
> ----- Original Message -----
> From: <ueda@xxxxxxxxxxxx>
> To: "silists" <si-list@xxxxxxxxxxxxx>
> Sent: Saturday, June 21, 2003 4:39 PM
> Subject: [SI-LIST] Damped voltage oscillation
>
>
> > Hi, ALL
> > Does anyone know the example which damped voltage oscillation?
> > The resistor is connected with the series in decoupling capacitor to
> insert
> > between power(vdd) and ground (gnd).
> > Don't you know the paper, the materials?
> > Chihiro Ueda
> > AET japan INC
> >
> >
> > *************************
> > Engineering Division
> > Chihiro Ueda
> > AET JAPAN, INC.
> > URSIS Bldg. 9th Floor
> > 1-2-3 Manpukuji, Asaoku,
> > Kawasaki-City,215-0004Japan
> > TEL:81-044-966-9981
> > FAX:81-044-951-1572
> > mailto:ueda@xxxxxxxxxxxx
> > http://www.aetjapan.com
> > *************************
> >
> >
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