[SI-LIST] Re: DVI compliance woes

  • From: "Tom Dagostino" <tom@xxxxxxxxxxxxxxxxx>
  • To: <andrew@xxxxxxxxxxxxxxxxxx>, "'SI-List'" <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 18 Feb 2015 10:07:39 -0800

There are input terminations on the PTN3360 that are turned on when OE_N is
low.

Tom Dagostino

Teraspeed Labs
9999 SW Wilshire Street
Suite 102
Portland, OR 97225

tom@xxxxxxxxxxxxxxxxx 
www.teraspeedlabs.com

971-279-5325 office
503-430-1065 cell


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Andrew Holme
Sent: Wednesday, February 18, 2015 12:34 AM
To: SI-List
Subject: [SI-LIST] DVI compliance woes

I'm performing DVI compliance testing on a board with ptn3360d TMDS level
shifters followed by WURTH 744233900 common mode chokes and RCLAMP0524P ESD
diodes.  I don't think the EMC/ESD components cause any problems; however,
the rise time of the level shifters makes reflections and crosstalk passing
through the DVI connectors, which is ruining the eye diagram.

I measure rise times of 90ps on a 13 GHz 'scope connected to my test
fixture.  This just seems unnecessarily fast.

75 ps < tr < 0.4*Tbit for compliance.

0.4*Tbit = 272 ps at 165 Mpixels.

To make matters worse, the ptn3360d does not terminate the pair, so
reflections are not absorbed at the driven end.

How does anyone ever pass the DVI compliance test with these connectors?

I think my only option is to try ~ 1pF parallel caps across the ptn3360d
output pins to see if I can slow down those edges.

Can anyone suggest anything else?

Thanks,
Andrew.


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