[SI-LIST] Re: DF spec for PCB materials
- From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- To: Istvan Nagy <buenos@xxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 16 Aug 2012 15:06:04 +0000
Good questions, some of which we haven't worked out all the details for every
design/vendor yet. But, I'll try to clarify some things, based on what I've
experienced.
Do you do this measurement on every batch of PCBs or every panel?
We have found that loss doesn't vary much between lots, so doesn't need to be
measured at anywhere near the frequency of impedance. Once you have found the
recipe that gives adequate loss, it seems to hold steady. Chu-tien (Jerry)
Chia, Richard Kunze, David Boggs, and Margaret Cromley did an excellent paper
on this entitled "A Study of PCB Insertion Loss Variation in Manufacturing
Using a New Low Cost Metrology", available on the web. One thing we're finding
on some stackups, however, is more variation, even between layers within a
stackup. For instance, on an 8 layer stackup, we have seen layers 3 and 6 have
significantly different loss (and/or coupling and/or propagation velocity!).
We didn't note this previously, and are working to understand it more.
On the same coupon as the impedance?
The SET2DIL coupon can be used to measure impedance, but we continue to have
dedicated impedance coupons, since they are much easier to measure quickly.
Who pays for the manufactured panels where the loss does not meet the specified
value?
Ideally, it will be handled just like impedance, but that might be a bit
optimistic at this point. Currently, we typically go through some iterations
with board vendors, building SET2DIL test boards which mimic our proposed
stackup and collaboratively modifying that stackup based on the SET2DIL
results. Once we find a "recipe" which meets our needs (with some tolerance),
we "lock down" that recipe and apply it to our product boards. Only a change
in the recipe should cause the loss value to change significantly, so I would
think the fab vendor would be responsible at that point (though it hasn't been
an issue, as far as I know). Soon, we hope that vendors will have the tools
and experience to be able to predict/monitor/control loss before building
boards (just as they predict impedance) and the onus will fall to them to meet
the loss requirement.
Often when a new type of requirement comes up, a lot of people especially at
the fab try the requirement to look illegitimate or ridiculous.
We have been working vigorously with vendors throughout the world to acquaint
them with the concept of insertion loss and how to control, measure, and
monitor it. You shouldn't have to go far to find a vendor who is intimately
familiar with insertion loss and/or SET2DIL. I'm sure there are some (perhaps
critical) vendors we've missed, but I believe the majority have some competence
in this area. We have had a spec. of approximately -0.8dB/inch @ 4GHz on many
designs for quite a while; if your spec. is no tighter than that, many folks
should be able to accommodate it w/o angst.
Regarding the channel between me and the fab and/or assembly houses - that
varies, depending on what "hat" I'm wearing at the moment, and who I'm dealing
with. Usually, however, I (or someone in my position) am (are?) working with
the fab vendors and assembly houses directly to work out details. But that
varies - Jerry Chia often provides invaluable
translation/clarification/follow-through for us when dealing with vendors, for
instance. One indication of how it's done is that my wife is not surprised
anymore by late night phone meetings speaking engineering nonsense for hours on
end...
Note: these are my own personal experiences/observations, and aren't intended
in any way to represent an "official" Intel position. In fact, we are learning
so many new things so quickly, I don't think it's possible to articulate rigid
policies at this point (for instance, periodicity of loss measurements).
P.S.
We try not to refer to it as "Intel's" SET2DIL method, though we originally
conceived it. It has now been adopted as an IPC standard (IPC-TM-650 Method
2.5.5.12, though I don't know if the rev. has been published yet), at least 2
vendors are supporting tools to measure it in HVM environments, and there are
other companies providing measurement services. It's been a wonderful child,
but it's time for it to leave the nest and visit the rest of the industry... :-)
Cheers,
Jeff Loyer
-----Original Message-----
From: buenos@xxxxxxxx [mailto:buenos@xxxxxxxx] On Behalf Of Istvan Nagy
Sent: Wednesday, August 15, 2012 8:49 PM
To: Loyer, Jeff; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: DF spec for PCB materials
Hi,
Thanks, actually it does help.
So I will focus on the typical value and try to get the FAB measure the loss
per unit length.
Eric Bogatin had an article where he referred to you and intel's method about
SET2DIL measurements.
Do you do this measurement on every batch of PCBs or every panel? On the same
coupon as the impedance?
The other interesting thing is who pays for the manufactured panels where the
loss does not meet the specified value... Often when a new type of requirement
comes up, a lot of people especially at the fab try the requirement to look
illegitimate or ridiculous. Wel, its a fight.
I will try to come up with some spec values for this.
I would not use microstrip for high speed, since all my designs are real
products and very dense as well, unlike reference designs where they have a lot
of space for routing on outer layers.
I am working with far east assembly company who is now standing between me and
the PCB fab, so the communication channel for this issue seem to have too much
dropped packets... I used to work at smaller companies in Europe, and always
dealt with the fabs myself. Do you do it directly, or through another company,
broker, other department...
Regards,
Istvan Nagy
Fortinet
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