[SI-LIST] Re: DDR-II: SSTL_18 & ODT
- From: pgregory <pgregory@xxxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 13 Aug 2002 15:37:49 -0600
JEDEC has two SSTL specs: SSTL_2 (2.5V) [JESD8-9B] and SSTL_3 (3.3V).
There is no SSTL_1 or SSTL_18 JEDEC spec.
The HSTL spec is a 1.5V spec [JESD8-6]. The industry has created a
defacto standard for HSTL operating at 1.8V (see Micron RLDRAM and
QDRII data sheets
http://download.micron.com/pdf/datasheets/sram/MT54W1MH18B_4.pdf )
On-die-termination has to balance many things including power and
SI. The non-ideal termination is a compromise. See
http://download.micron.com/pdf/technotes/TN4606.pdf for a look
at some comparison values.
-----Original Message-----
From: Bret Stott [mailto:bstott@xxxxxxxxxxxxxxxx]
Sent: Monday, August 12, 2002 12:35 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR-II: SSTL_18 & ODT
Hi SI-gurus,
I am a new member of this list and I have a few questions about DDR-II that
I
was hoping someone could help me out with. Currently, I don't have access
to
JEDEC so most of my information is from alternate sources such as the
Samsung
DDR-II spec.
o Can anyone point me at a SSTL_18 specification?
o Can someone help me understand the on-die-termination strategy for DDR-II?
Why are the values 75 & 150 Ohms? What electrical topology is being
assumed?
o My initial analysis suggests that it is possible to use class I drivers
for
the address bus (5 load) and also for a point-to-point data bus. The data
bus
may require some non-standard termination values though. Does anyone have
any
information that supports of refutes this?
Thanks in advance,
-Bret
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