[SI-LIST] DDR-II: SSTL_18 & ODT
- From: Bret Stott <bstott@xxxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 12 Aug 2002 11:35:11 -0700
Hi SI-gurus,
I am a new member of this list and I have a few questions about DDR-II that I
was hoping someone could help me out with. Currently, I don't have access to
JEDEC so most of my information is from alternate sources such as the Samsung
DDR-II spec.
o Can anyone point me at a SSTL_18 specification?
o Can someone help me understand the on-die-termination strategy for DDR-II?
Why are the values 75 & 150 Ohms? What electrical topology is being assumed?
o My initial analysis suggests that it is possible to use class I drivers for
the address bus (5 load) and also for a point-to-point data bus. The data bus
may require some non-standard termination values though. Does anyone have any
information that supports of refutes this?
Thanks in advance,
-Bret
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