[SI-LIST] Re: DDR-II

  • From: James Church <jchurch@xxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Wed, 30 Mar 2005 12:13:58 -0800

Prakash,

The question is what are you trying to achieve in your simulations. Are 
you trying to get extremely detailed timing relationships for the entire 
bus? Then you probably need the entire setup running in spice. You might 
retire on this one project alone!  I don't know that spice can handle 
running the entire system you are describing if you consider 3D 
extracted packages with ground/power nets, on chip parasitics 
(controller and memory), board crosstalk effects, vias, frequency 
dependant inductance/capacitance, trace mismatch, and multiline 
connector models (something that accounts for crosstalk and power plane 
discontinuity). That doesn't even begin to attack the problem of power 
distribution on the board.  It might be less time consuming to just 
build and debug the board blindly.  This simulation, if it converged, 
might run for a week or 2 or 3.  It's still a shot in the dark because 
you have to assume that everything "macromodels" correctly. i.e. 
attaching the connector to the board in spice has the same effect as 
soldering it to the board in real life (not likely).

Can you live with cutting the simulation down to single ~9 bit DQ/DQS 
chunks and simulating with SSO and package-board crosstalk effects? The 
timing is most critical between the DQ and their associated DQS/DM bits. 
There is more leeway with the overall system. So maybe you can guarantee 
the most critical timing with spice and run the larger system timing 
with IBIS and one of the larger system level simulation tools.  It's 
kind of a distributed attack to the problem.  You won't get the timing 
accuracy with the IBIS that you would get in hspice, but you may not 
need it if you build margin into your system. I don't know that it saves 
you any setup time. You now have multiple tools and multiple models, 
however, it may save you loads of simulation time. Still there's an 
element of risk you will live with.  You can at least simulate the macro 
level parameters (clock distribution, ODT settings, drive strength 
settings) to get an idea of what works best, before you simulate the 
micro level parameters (xtalk, SSO, parasitics).

The hole in this approach is that you have to be comfortable that at the 
end, everything fits together. 

These are my personal suggestions, good luck.

James




Prakash N wrote:

>Hi 
>When doing our interface design the problem is like this.
>We are having seperate 16 bit data for read and write at the controller side 
>and 8 bit bidirectional data at the memory side. Our interface has some mux, 
>OCD , ODT etc. Actually we are not doing full controller design rather I/O 
>part of controller. So while simulating we are not giving address,RAS,CAS 
>etc,. Only we are having data bits, OE and control bits for OCD,ODT. Now if we 
>want to simulate the interface there are so many combinations we have to try, 
>as effectively 32 bit data (seperate 16 bit data for read and write) is 
>connected to 8-bit data. This simulation takes more time and laborius. Could 
>anyone suggest how to test effectively so that the time and complexity is 
>reduced.
> 
>My second question is 
>should we have to put ODT (On-Die termination) on both transmitter and 
>reciever (both on controller) or it is enough to have ODT in reciever side, as 
>there is a OCD(off-chip driver) in transmitter side which can take care of 
>termination.
> 
>Regards
>Prakash
>
>Kai Keskinen <kalevi@xxxxxxxxxx> wrote:
>Simulating 8 bits plus associated clock, address, and strobe should take
>about 1 hour to set up and 10 minutes to simulate with an IBIS simulator
>like Allegro PCB SI or Mentor's Hyperlynx. What tool are you using? Even
>with HSPICE, the set up will take a bit longer but you should be able to
>simulate in no more than 1 hour (and probably a lot less) unless you have
>very low level encrypted spice models.
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Prakash N
>Sent: Tuesday, March 29, 2005 10:32 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] DDR-II
>
>
>Hi
>I'm doing mini project in DDR-II interface between controller and DDR-II.
>Anybody knows how to simulate, as trying to simulate 8 bits will take a
>long time. So we have to simplify the simulation with good accuracy. If
>anyone knows about simultaing , please help me.
>Regards
>Prakash
>
>
>M.E.(Microelectronics Systems)
>
>Centre for Electronics Design & Technology (CEDT)
>
>Indian Institute of Science, Bangalore-560012
>
>Karnataka-India
>
>09448787632
>
>
>Yahoo! India Matrimony: Find your life partneronline.
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