[SI-LIST] DDR4 and PAM4 DesignCon papers

From: <colin_warwick@xxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Wed, 11 Feb 2015 21:52:29 +0000

Hi si-listers,

I uploaded our DesignCon 2015 technical track papers to:

http://signal-integrity.blogs.keysight.com/2015/designcon-2015-papers-from-eesof-co-authors/

* Ultrascale DDR4 De-emphasis and CTLE Feature Optimization with Statistical 
Engine for BER Specification
* IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems

It also has the slides from a tutorial and a panel we did.

Thanks to our co-authors at Xilinx, Speeding Edge, and Wild River Labs.

Best regards,

-- Colin
____________________
Colin Warwick
Product Manager
Keysight EEsof EDA

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[SI-LIST] DDR4 and PAM4 DesignCon papers

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