[SI-LIST] Re: DDR3 termination with only 2 memory devices

  • From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Sat, 21 Jan 2012 10:31:41 +0100

Hi,

we have just done a similar setup with LPDDR2 devices.

Starting with "Quick" simulations it turned out, that especially the
Read was critical.
After starting with some "Quick" simulation we ended up in doing Full
corner case evaluation, Stackup impedance optimizaton and Timing budget
calculation to ensure a stable system for HVM.
Of course this depends on the exact configuration, but doing a "Quick"
simulation might not be enough ...

Hermann



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schrieb Stephanie Goedecke:
> That is, 303-400 MHz clock rate, so up to 800 MHz data rate.  It would 
> be great if you have time to run a quick simulation on this.
>
> On 1/20/2012 1:03 PM, Stephanie Goedecke wrote:
>> 303-400 MHz.  Thanks for looking at this.
>>
>> On 1/20/2012 12:51 PM, Syed Bokhari wrote:
>>> Hi Stephanie,
>>>
>>> What data rate/speed are you expecting? If you are pushing it to the 
>>> limit,
>>> I would say use the pull up termination.  If not, the series resistor is
>>> Acceptable.
>>>
>>> If you wish, we can do a quick simulation for you...........
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> Syed Bokhari, Ph.D
>>>         Fidus Systems Inc.
>>>
>>> syed.bokhari@xxxxxxxx
>>> 900, Morrison Drive
>>>
>>> Tel: (613) 828 - 0063 x 377   Ottawa, Ontario
>>>
>>> Fax:(613) 828-3113
>>> Canada, K2H 8K7
>>>
>>> www.fidus.ca
>>>
>>>
>>> -----Original Message-----
>>> From: si-list-bounce@xxxxxxxxxxxxx 
>>> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Stephanie Goedecke
>>> Sent: January-20-12 3:39 PM
>>> To: si-list@xxxxxxxxxxxxx
>>> Subject: [SI-LIST] DDR3 termination with only 2 memory devices
>>>
>>> Hi Experts,
>>> I don't have access to simulation tools right now.  If any of you 
>>> have thoughts about a termination plan for a DDR3 bus I'm looking at, 
>>> please let me know.
>>> The bus is 16-bits wide.  It will support 2x 8-bit devices (not 2 
>>> dimms).  The processor is a Texas Instruments AM3359 processor.  The 
>>> TI datasheet for this processor recommends making a VTT-rail and 
>>> parallel termination, like with DDR3 dimms.  This seems like overkill 
>>> with only 2 devices.  The layout is very space-constrained.  I would 
>>> rather use serial termination if it would work for lower power&  
>>> noise, fewer components, and simpler layout.
>>>
>>> There is a technical note from Micron (Technical Note TN-46-14) that 
>>> recommends parallel termination over serial termination for DDR3 
>>> buses if at least one of the following applies:
>>>
>>>      1. five or more DDR devices
>>>      2.>2in trace lengths
>>>      3. poor simulation results
>>>      4. errors during prototyping
>>>
>>> There are only 2 DDR devices and<  2 in trace lengths.  I don't have 
>>> simulation or prototypes.  I would like to plan to use serial 
>>> termination, but I'd feel a lot better about deciding this against 
>>> the TI datasheet recommendations if somebody has simulation or lab 
>>> experience with a similar bus.  Do any you?  Please let me know what 
>>> you think.
>>>
>>> thanks,
>>> Stephanie
>>>
>>>
>>>
>>>
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