[SI-LIST] Re: DDR3 termination with only 2 memory devices
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 20 Jan 2012 14:52:10 -0800
Stephanie your best bet is to pay any of the many shops out there to do
that part of your design and put it through simulation. Then you will
have something that works in a timely and cost effective manner.
Steve
On 1/20/2012 12:38 PM, Stephanie Goedecke wrote:
> Hi Experts,
> I don't have access to simulation tools right now. If any of you have
> thoughts about a termination plan for a DDR3 bus I'm looking at, please
> let me know.
> The bus is 16-bits wide. It will support 2x 8-bit devices (not 2
> dimms). The processor is a Texas Instruments AM3359 processor. The TI
> datasheet for this processor recommends making a VTT-rail and parallel
> termination, like with DDR3 dimms. This seems like overkill with only 2
> devices. The layout is very space-constrained. I would rather use
> serial termination if it would work for lower power& noise, fewer
> components, and simpler layout.
>
> There is a technical note from Micron (Technical Note TN-46-14) that
> recommends parallel termination over serial termination for DDR3 buses
> if at least one of the following applies:
>
> 1. five or more DDR devices
> 2.>2in trace lengths
> 3. poor simulation results
> 4. errors during prototyping
>
> There are only 2 DDR devices and< 2 in trace lengths. I don't have
> simulation or prototypes. I would like to plan to use serial
> termination, but I'd feel a lot better about deciding this against the
> TI datasheet recommendations if somebody has simulation or lab
> experience with a similar bus. Do any you? Please let me know what you
> think.
>
> thanks,
> Stephanie
>
>
>
>
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