[SI-LIST] Re: DDR3 read bit-deskew training mechanism

  • From: jackle zheng <zheng.jackle@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Wed, 14 Nov 2012 17:59:40 +0800

hi, Steve Istvan
thanks your immediate reply.
just as your said, the read bit-deskew training algorithm equips many delay
line elements to tuning the each DQ's read path which is from MEM to
controller to eliminate skew. The aim is to align the edge of each DQ
signal within one byte lane. The question is how to do to align these edge.
Are there any other algorithms can do bit-deskew among the eight DQ signals?
2012/11/14 Istvan Nagy <buenos@xxxxxxxxxxx>

> Hi
>
> The implementation is normally non-standard.
> Here I mentioned a few:
> http://pcdandf.com/cms/**component/content/article/171-**
> current-issue/7562-signal-**integrity<http://pcdandf.com/cms/component/content/article/171-current-issue/7562-signal-integrity>
> At the section about "Timing calibration".
>
> Regards,
> Istvan Nagy
>
> -----Original Message----- From: jackle zheng
> Sent: Tuesday, November 13, 2012 1:08 AM
> To: Hermann.Ruckerbauer@**eyeknowhow.de<Hermann.Ruckerbauer@xxxxxxxxxxxxx>
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR3 read bit-deskew training mechanism
>
>
> hi, Hermann & members,
> i am reading some vendor DDR3 IP spec. At DDR data training section, i
> can't  understand its mechanism about how to align the edge of bits within
> 1 byte lane. And i browse the JEDEC-3E spec, there was also no answer.
> So, i want to know there are some common mechanism about how to eliminate
> the bit deskew .
> --
> i am here because i am thinking
>
>
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