[SI-LIST] Re: DDR3 read bit-deskew training mechanism

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Tue, 13 Nov 2012 04:12:53 -0800

The method is up to the ASIC designer. Tapped delay lines are common.

Steve.
On 11/13/2012 1:08 AM, jackle zheng wrote:
> hi, Hermann & members,
> i am reading some vendor DDR3 IP spec. At DDR data training section, i
> can't  understand its mechanism about how to align the edge of bits within
> 1 byte lane. And i browse the JEDEC-3E spec, there was also no answer.
> So, i want to know there are some common mechanism about how to eliminate
> the bit deskew .


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