The method is up to the ASIC designer. Tapped delay lines are common. Steve. On 11/13/2012 1:08 AM, jackle zheng wrote: > hi, Hermann & members, > i am reading some vendor DDR3 IP spec. At DDR data training section, i > can't understand its mechanism about how to align the edge of bits within > 1 byte lane. And i browse the JEDEC-3E spec, there was also no answer. > So, i want to know there are some common mechanism about how to eliminate > the bit deskew . -- Steve Weir IPBLOX, LLC 150 N. Center St. #211 Reno, NV 89501 www.ipblox.com (775) 299-4236 Business (866) 675-4630 Toll-free (707) 780-1951 Fax All contents Copyright (c)2012 IPBLOX, LLC. All Rights Reserved. This e-mail may contain confidential material. If you are not the intended recipient, please destroy all records and notify the sender. ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List forum is accessible at: http://tech.groups.yahoo.com/group/si-list List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu