Vinod, Unless I'm missing something, I doubt the spectrum analyzer display you see is Hyperlynx has anything to do with radiation. I think that's just an FFT of the simulated waveform - it tells you frequency content and magnitude, but not whether any of that energy will radiate. You have to understand how each element of the physical structure interacts with the EM field in and around it to predict that, and I don't think the tool you're using does that. It's kind of like a "I have this much water in a box, will it leak?" problem. If you don't know anything about the box, there's no way of telling if any of the water will escape. My $0.02. Todd. -- Todd Westerhoff VP, Software Products SiSoft 6 Clock Tower Place, Suite 250 Maynard, MA 01754 (978) 461-0449 x24 twesterh@xxxxxxxxxx www.sisoft.com "It doesn't matter what you've heard Impossible is not a word It's just a reason For someone not to try" -Kutless -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of vinod ah Sent: Saturday, January 07, 2012 12:28 AM To: SI-LIST Subject: [SI-LIST] DDR3 clock failing radiation Tests Hi all, I am facing problems related to EMI. I am having a ASIC with 2 DDR3 controllers running at 513MHz clock. I am interfacing 2 memories to each of the controller. So totally 4 memory chips on board, all running at 513MHz clock. During pre-compliance radiation testing in FCC certified lab, we observed 513MHz in the spectrum with 15dB above the CISPR class B limits i.e. test failing by 15dB !!!!! I tried to corelate this result with Hyperlynx spectrum analyzer simulation and SI simulation. The waveforms and radiation level looks fine in Hyperlynx i.e. no issues seen. Initially i had suspected the layout, but hyperlynx SI simulation looks fine and also the clock & dqs waveforms in CRO looks fine i.e. no ringing/overshoot etc. The DDR3 clock is routed in inner layer 3 of six layer stack up of the board. I have tried using EMI shield, but still i am failing by 8dB. Only thing i have not yet tried is spread spectrum clocking. But I am unable to find the source of problem. Can you please help me out in finding the sourceto this problem. I understand that it is very tuff to provide solution to this problem without seeing the layout, but i am expecting some tips so that i can move ahead in debugging the problem. Regards Vinod A H ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu