[SI-LIST] Re: DDR3 clock failing radiation Tests

  • From: vinod ah <ah.vinod@xxxxxxxxx>
  • To: doug@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Sat, 7 Jan 2012 12:04:07 +0530

Hi,
To nail down the issue, i had used magnetic near field probes to find out
where the radiation is maximum on the board. To my surprise, when i keep
the near field probe on top of processor/ASIC, the radiation is at its peak
when compared to keeping near field probes on top of traces or memory ic's.
In fact the radiation level is 30dB more on top of processor !!!!. So can
we conclude something based on this observations?

Regarding the clock routing, the clock lines are routed in daisy chain
fashion to 2 memories and have a thevenin termination of 47 ohms i.e. 47
ohms pulled up to VTT.  Since the ASIC is having high density BGA package,
the clock likes are routed to the bottom and then taken to inner layer and
then to top layer where it is terminated to VTT. There is solid ground
planes on layer 2 and layer 5 (6 layer stack up used). Near by ground vias
are present but not very near due to layout constraints and board size
constraints.

Regards
Vinod A H

On Sat, Jan 7, 2012 at 11:38 AM, Doug Smith <doug@xxxxxxxxxx> wrote:

> Hi Vinod,
>
> It is no surprise that the simulation did not show anything. Did you model
> the system enclosure with all its cavity resonances as well as slots,
> seams, and all the cables as well? I think it is nearly impossible to
> simulate the complete system to predict radiation. I view simulations as a
> way to evaluate simple structures to understand how emissions occur and
> then use that knowledge in combination with factors that are not easy to
> simulate to estimate emissions.
>
> It takes so little energy extracted from a signal to cause an emissions
> problem it is quite possible to have great looking waveforms and still have
> an emissions problem. I do an experiment in one of my seminars where the
> waveform at the end of the structure looks really good, but the structure
> fails emissions by something like 40 dB! For instance, is the risetime of a
> clock just slightly slower than one would expect? Where did that high
> frequency energy go? Possibly into emissions due to a layout issue.
> Although some waveform anomalies definitely can cause EMC problems, a great
> looking waveform may still be a problem.
>
> ICs couple strongly to any nearby conductors which then radiate nicely
> where the IC would have been too small physically to be a problem on its
> own.
>
> Of course, board layout issues are another possibility.
>
> Knowing how the emissions get out into the wild can often help in tracking
> down the source. Measurements involving wire loops (fancy name = magnetic
> field probes), current probes, network analyzers or spectrum analyzers with
> directional couplers to measure resonances of physical structures, and so
> on.
>
> There are so many possibilities for your case, much more detail would be
> needed to avoid having you waste you time on a "wild goose chase." Of
> course another possibility is there is a common problem in the circuits you
> are working with that causes the emissions problem and is easy to avoid.
> Generally, one is really lucky if this is the case, but if it exists there
> are probably a number of people on this list that can help.
>
> Doug
>
>
> On 1/6/12 9:27 PM, vinod ah wrote:
>
>> Hi all,
>> I am facing problems related to EMI. I am having a ASIC with 2 DDR3
>> controllers running at 513MHz clock. I am interfacing 2 memories to each
>> of
>> the controller. So totally 4 memory chips on board, all running at 513MHz
>> clock. During pre-compliance radiation testing in FCC certified lab, we
>> observed 513MHz in the spectrum with 15dB above the CISPR class B limits
>> i.e. test failing by 15dB !!!!!
>>
>> I tried to corelate this result with Hyperlynx spectrum analyzer
>> simulation
>> and SI simulation. The waveforms and radiation level looks fine in
>> Hyperlynx i.e. no issues seen. Initially i had suspected the layout, but
>> hyperlynx SI simulation looks fine and also the clock&  dqs waveforms in
>>
>> CRO looks fine i.e. no ringing/overshoot etc. The DDR3 clock is routed in
>> inner layer 3 of six layer stack up of the board.
>>
>> I have tried using EMI shield, but still i am failing by 8dB. Only thing i
>> have not yet tried is spread spectrum clocking. But I am unable to find
>> the
>> source of problem. Can you please help me out in finding the sourceto this
>> problem.
>>
>> I understand that it is very tuff to provide solution to this problem
>> without seeing the layout, but i am expecting some tips so that i can move
>> ahead in debugging the problem.
>>
>> Regards
>> Vinod A H
>>
>>
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