[SI-LIST] Re: DDR3 clock failing radiation Tests

  • From: alan@xxxxxxxxxxxxxxxxx
  • To: "vinod ah"<ah.vinod@xxxxxxxxx>, SI-LIST<si-list@xxxxxxxxxxxxx>
  • Date: Fri, 6 Jan 2012 21:49:36 -0800

Vinod,
Many possibilities come to mind, but since the failing frequency is at the  
clock frequency, my first question would be: how are the clock lines  
terminated?

I would also be looking at the routing - do the clocks cross any plane  
breaks? Do the clocks change layers? Do the transition vias have  
accompanying ground return vias?

You need to follow not just the routing, but also the associated return  
currents to look for inductive loops.

Alan Hilton-Nickel
Oracle Corp

Sent from my Verizon Wireless 4G LTE Phone

-----Original message-----
From: vinod ah <ah.vinod@xxxxxxxxx>
To: SI-LIST <si-list@xxxxxxxxxxxxx>
Sent: Fri, Jan 6, 2012 21:27:34 PST
Subject: [SI-LIST] DDR3 clock failing radiation Tests

Hi all,
I am facing problems related to EMI. I am having a ASIC with 2 DDR3
controllers running at 513MHz clock. I am interfacing 2 memories to each of
the controller. So totally 4 memory chips on board, all running at 513MHz
clock. During pre-compliance radiation testing in FCC certified lab, we
observed 513MHz in the spectrum with 15dB above the CISPR class B limits
i.e. test failing by 15dB !!!!!

I tried to corelate this result with Hyperlynx spectrum analyzer simulation
and SI simulation. The waveforms and radiation level looks fine in
Hyperlynx i.e. no issues seen. Initially i had suspected the layout, but
hyperlynx SI simulation looks fine and also the clock & dqs waveforms in
CRO looks fine i.e. no ringing/overshoot etc. The DDR3 clock is routed in
inner layer 3 of six layer stack up of the board.

I have tried using EMI shield, but still i am failing by 8dB. Only thing i
have not yet tried is spread spectrum clocking. But I am unable to find the
source of problem. Can you please help me out in finding the sourceto this
problem.

I understand that it is very tuff to provide solution to this problem
without seeing the layout, but i am expecting some tips so that i can move
ahead in debugging the problem.

Regards
Vinod A H


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