[SI-LIST] DDR3 clock failing radiation Tests

  • From: vinod ah <ah.vinod@xxxxxxxxx>
  • To: SI-LIST <si-list@xxxxxxxxxxxxx>
  • Date: Sat, 7 Jan 2012 10:57:34 +0530

Hi all,
I am facing problems related to EMI. I am having a ASIC with 2 DDR3
controllers running at 513MHz clock. I am interfacing 2 memories to each of
the controller. So totally 4 memory chips on board, all running at 513MHz
clock. During pre-compliance radiation testing in FCC certified lab, we
observed 513MHz in the spectrum with 15dB above the CISPR class B limits
i.e. test failing by 15dB !!!!!

I tried to corelate this result with Hyperlynx spectrum analyzer simulation
and SI simulation. The waveforms and radiation level looks fine in
Hyperlynx i.e. no issues seen. Initially i had suspected the layout, but
hyperlynx SI simulation looks fine and also the clock & dqs waveforms in
CRO looks fine i.e. no ringing/overshoot etc. The DDR3 clock is routed in
inner layer 3 of six layer stack up of the board.

I have tried using EMI shield, but still i am failing by 8dB. Only thing i
have not yet tried is spread spectrum clocking. But I am unable to find the
source of problem. Can you please help me out in finding the sourceto this
problem.

I understand that it is very tuff to provide solution to this problem
without seeing the layout, but i am expecting some tips so that i can move
ahead in debugging the problem.

Regards
Vinod A H


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