[SI-LIST] Re: DDR3 VTT Bypassing
- From: Don Nelson <dhwn@xxxxxxx>
- To: stefan.milnor@xxxxxxxxxxxxxx
- Date: Sat, 08 Sep 2012 22:20:59 -0400
The JEDEC spec for referencing A/C to 1.5V relates to DIMMs only, AFAIK. The
A/C signals on the edge connector are nearest the 1.5V fingers and the A/C
traces are referenced to 1.5V planes on the DIMM PCB.
As for VTT, I'm not familiar with the advice of decoupling to Vdd rather than
to GND, but if the PDN has a low enough impedance across the relevant
frequencies, I'm not sure it will matter. I'd love to be enlightened, though.
--
Don Nelson
Sent with Sparrow (http://www.sparrowmailapp.com/?sig)
On Saturday, September 8, 2012 at 9:22 PM, Stefan Milnor wrote:
> And the SOC vendor says all memory signals (including A/C) should be GND
> referenced. But same vendor's FAE says VTT bypass should be to 1.5V. Hence
> the question to this august list.
>
> On Sep 8, 2012, at 6:15 PM, "Stefan Milnor" <stefan.milnor@xxxxxxxxxxxxxx>
> wrote:
>
> > According to whom, or to what spec? This is not an SO-DIMM situation, it is
> > memory down, next to the SOC.
> >
> > On Sep 8, 2012, at 4:37 PM, "steve weir" <weirsi@xxxxxxxxxx> wrote:
> >
> > > Data signals are supposed to run against GND. A/C are supposed to run
> > > against VDD.
> > >
> > > Steve
> > > On 9/8/2012 7:19 AM, Stefan Milnor wrote:
> > > > But they are not against VDD, they are against GND. Hence my question;
> > > > are we getting conflicting advice from the vendor (route signals
> > > > against GND but bypass VTT to VDD)
> > > >
> > > > On Sep 7, 2012, at 10:55 PM, "steve weir" <weirsi@xxxxxxxxxx> wrote:
> > > >
> > > > > d) makes sense if you are also routing according to the
> > > > > recommendations,
> > > > > which runs A/C against VDD in the PCB.
> > > > >
> > > > > Steve
> > > > > On 9/7/2012 10:17 PM, Stefan Milnor wrote:
> > > > > > Experts -
> > > > > >
> > > > > >
> > > > > > For a DDR3 interface, for an SOC from a vendor that you all have
> > > > > > heard
> > > > > > of, we are being advised to:
> > > > > >
> > > > > >
> > > > > >
> > > > > > a) Reference all DDR3 signals to GND
> > > > > >
> > > > > > b) Terminate certain signals at the far end, to VTT (0.75V)
> > > > > >
> > > > > > c) Make sure the VTT supply can sink and source current
> > > > > >
> > > > > > d) Bypass the VTT supply with caps from VTT to VDD (1.5V) (and not
> > > > > > to GND)
> > > > > >
> > > > > >
> > > > > >
> > > > > > Does item d) make sense, if the signals are GND referenced?
> > > > > > Wouldn't it
> > > > > > make more sense if those signals we referenced against VDD?
> > > > > >
> > > > > >
> > > > > >
> > > > > > The vendor's rationale for bypassing with caps from VTT to VDD is
> > > > > > quoted
> > > > > > as follows:
> > > > > >
> > > > > >
> > > > > >
> > > > > > "The reason for bypassing to 1.5V instead of GND is that VTT is both
> > > > > > sinking and sourcing current. When high side mosfet of the buffer is
> > > > > > turned ON, for logic HI, the current flow is from 1.5V to MOSFET to
> > > > > > termination resistor to VTT power supply. Signal is switched
> > > > > > referenced
> > > > > > to VTT, so we need to decouple the buffer's 1.5V pin to VTT, not to
> > > > > > GND.
> > > > > >
> > > > > > No need for the decap between buffer's GND to VTT, because GND is
> > > > > > much
> > > > > > more robust than 1.5V rail (usually a massive plain) and can supply
> > > > > > necessary instantaneous current for logic LOW."
> > > > > >
> > > > > >
> > > > > >
> > > > > > What do you think?
> > > > > >
> > > > > >
> > > > > >
> > > > > > Thanks, Stefan M.
> > > > > >
> > > > > >
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> > > > >
> > > > > --
> > > > > Steve Weir
> > > > > IPBLOX, LLC
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> > > --
> > > Steve Weir
> > > IPBLOX, LLC
> > > 150 N. Center St. #211
> > > Reno, NV 89501
> > > www.ipblox.com
> > >
> > > (775) 299-4236 Business
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