[SI-LIST] DDR3 VTT Accuracy Requirements
- From: Hirshtal Itzhak <ihirshtal@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 22 Mar 2010 15:48:35 +0200
Hello,
I've noticed lately that VTT specification for the DDR3 SDRAM devices is
not defined as was VTT for DDR2 devices.
For the DDR2 devices it was required to be no further than 40mV from
VREF.
In the DDR3 spec this requirement has been removed and instead a note
says that the MIN & MAX values for this supply are system dependent.
What system considerations are to be applied for VTT tolerance? The only
thing that comes to my mind is the timing of the ADR/CMD signals. Would
simulations with the "skewed" VTT be enough to evaluate the impact of
certain VTT in-accuracies? Can I assume (as a 1st degree assumption)
that the in-accuracy of VTT will be directly reflected in the threshold
levels of the device?
And are there other considerations to be taken?
Thanks in advance
Itzhak Hirshtal
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