[SI-LIST] Re: DDR3 Slew Rate derating.

  • From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Tue, 26 Jan 2010 07:23:16 +0100

Hi,

describing this in words is always quite difficult. I would have some
slides with animations, and if some more people are interested I could
show this in a short Webmeeting (hoping the animations would work there).
I have only capability for doing small webmeetings, so if someone would
volunteer to set a meeting up this would be great.
Let me know if somebody is interested.

Hermann



EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
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94554 Moos
Tel.:   +49 (0)9938 / 902 083
Mobile: +49 (0)176  / 787 787 77
Fax:    +49 (0)3212 / 121 9008


schrieb Moran, Brian P:
> Surita,
>
> Let me try to give you a quick tutorial on derating, which should answer
> your question. Please follow up if I don't answer your question fully.
>
> Derating consists of two components. There is the reciever derating at Vref,
> which tends to be 0ps at 1V/ns and above, and then increases as slew rate 
> slows.
> This accounts for the fact that the SDRAM reciever timing starts to degrade as
> slew rate drops below 1V/ns. It's a function of the reciever design, and this
> derating at Vref curve is defined by the SDRAM vendors. It has not chnaged
> significantly since DDR2. The second component of derating is threshold 
> compensation.
> This only comes into play when you measure flight times to AC or DC 
> thresholds. 
> Measuring to the AC or DC thresholds tends to distort the flight time 
> measurements. 
> This type of derating is dependent on threshold level, which si why you get 
> different
> derating tables as speed bin increases. Its not the speed the matetrs, but 
> the AC
> abd DC thresholds. So what the JEDEC task group did was to apply a fixed 
> adjustment
> to the tSU and tHD specs at Vref, to account for this distortion at AC and DC.
> This adjustment is based on an input slew rate of 1V/ns.  So if your tSU at 
> Vref was
> 500 ps, and your AC threshold is 175 mV, the tSU at AC is 325 ps.  ON the 
> hold side,
> if your tHD was 500 ps at Vref, then tHD at DC is 400 ps.  They have 
> pre-biased
> the tSU by 175ps to compensate for the additioanl flight time caused by 
> measuring
> to AC175, vs Vref. 
>
> One quick thought exercise is to note that the margin calculated at Vref and 
> that
> calculated at AC threshold, for the same linear non-ledging signal should be 
> equal.
> This goes back to when you had the option of measuring to Vref or to AC/DC. 
>
> Ok, since they pre-biased the tSU spec by 175ps to account for AC threshold 
> distortion
> in your flight time, what happens if your slew rate was actually 2V/ns. That 
> means they
> pre-biased too much and have to take some back. This is where the +88ps comes 
> from. If
> the slew rate was 0.5V/ns then they did not compensate enough and you will 
> get negative
> numbers in the threshold compensation table at SRs less than 1V/ns. 
>
> The composite derating table shown in the JEDEC spec is the sum of the 
> reciever derating
> at Vref plus the threshold compensation. Threshold compensation is a purely 
> algebraic
> formula, which is; 175ps - 175mV/SR for an AC threshold of 175mV. The final 
> derating table
> is characterized by having 0 at 1V/ns, then increasingly positive numbers at 
> SRs above 1V/ns
> and increasingly negative at SRs below 1V/ns. This trend is beginning to 
> break as we get to
> smaller and smaller AC thresholds, but for now it's a simpe rule of thumb.
>
> Also note that a positive number in the derating tbale always reduces margin, 
> and visa versa.
>
> Like I said, follow up with another emial if its not clear. I consider myself 
> pretty
> knowledgable on derating and can provide some supporting docs if needed. 
>
>
> Brian Moran
> Signaling Development Group
> Client Platforms
> Intel Corporation
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
> Behalf Of Surita Chandani
> Sent: Monday, January 25, 2010 2:15 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR3 Slew Rate derating.
>
>
>
>
> I am trying to understand DDR3 slew rate derating. Let
> us say we are working with a differential DQS with a fixed slew rate of 2.0
> V/ns.
>
>  
>
> When the DQ slew rate is 1.5 V/ns the setup time is 59
> ps. When the DQ slew rate increases to 2.0 V/ns, the setup time increases to 
> 88
> ps. I thought the setup time would go down with a faster signal.
>
>
>
>
>       
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