[SI-LIST] Re: DDR3 Slew Rate derating.
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: Hirshtal Itzhak <ihirshtal@xxxxxxxxxx>, Lucian Zhang <zhanglub@xxxxxxxxxx>
- Date: Mon, 15 Feb 2010 21:08:58 -0700
Yes, the derating tables for tDS/tDH, based on DQ SR and DQS Diff SR, are
identical to the
tables for tIS/tIH, based on CTRL/CMD/ADR SR and CLK Diff SR. There are at
times been
formating differences in how the tables appeared in the spec, but the derating
formulas
themselves are identical.
Brian Moran
Signaling Development Group
Client Platforms
Intel Corporation
-----Original Message-----
From: Hirshtal Itzhak [mailto:ihirshtal@xxxxxxxxxx]
Sent: Monday, February 15, 2010 2:02 AM
To: Moran, Brian P; Lucian Zhang
Cc: Hermann Ruckerbauer; si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx;
sreekanth soman
Subject: RE: [SI-LIST] Re: DDR3 Slew Rate derating.
Hello Moran
Do your formulas apply to the ADDR/CMD signals and the differential CLK as well?
Thanks in advance
Itzhak Hirshtal
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Moran, Brian P
Sent: Friday, February 05, 2010 4:42 AM
To: Lucian Zhang
Cc: Hermann Ruckerbauer; si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx;
sreekanth soman
Subject: [SI-LIST] Re: DDR3 Slew Rate derating.
Lucian,
The formulas are based on single ended DQ slew rate. As I mentioned, they only
apply to slew rates of 1V/ns or higher, and likewise they apply to DQS
differential slew rates of 2V/ns or higher. However, you will notice if you
look at the JEDEC derating table that additional derating in the DQS axis is a
fixed value for every 0.2V/ns reduction in differential SR. You can use the
formulas to extend the derating tables on the left hand side up to higher DQ
slew rates, then simply apply the same fixed additional derating based on DQS
slew rate, as you move from left to right across the table.
These formulas actually apply throughout the DQ slew rate range, and represent
what is termed threshold compensation, however, as I mentioned in a previous
posting, below 1V/ns there is additional derating based on the actual timing
characteristics of the receiver at Vref, which are added to the total derating
value. However, this component of deratiiing is always zero at 1V/ns and
above, so all you have left is the threshold compensation, which is defined by
the formulas I posted. Hope this helps people better understand DDR3 derating.
It's a complicated topic and JEDEC could have done a better job of explaining
its derivation.
Brian Moran
Signaling Development Group
Client Platforms
Intel Corporation
-----Original Message-----
From: Lucian Zhang [mailto:zhanglub@xxxxxxxxxx]
Sent: Thursday, February 04, 2010 5:13 PM
To: Moran, Brian P
Cc: Moran, Brian P; Hermann Ruckerbauer; si-list@xxxxxxxxxxxxx;
si-list-bounce@xxxxxxxxxxxxx; sreekanth soman
Subject: Re: [SI-LIST] Re: DDR3 Slew Rate derating.
Brian,
The derating table is about DQ and DQS slew rate, so, there should be 2
veriables in your formulas.
Another question, is the SR in the formulas about DQ slew rate?
Thank you!
Lucian
"Moran, Brian P" <brian.p.moran@xxxxxxxxx>
Sent by: si-list-bounce@xxxxxxxxxxxxx
2010-02-05 02:01
To
"Moran, Brian P" <brian.p.moran@xxxxxxxxx>, sreekanth soman
<sreekanths18@xxxxxxxxx>, Hermann Ruckerbauer
<hermann.ruckerbauer@xxxxxxxxxxxxx>
cc
"si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Subject
[SI-LIST] Re: DDR3 Slew Rate derating.
Soman,
I just realized there is another point to be made regarding your question.
The derating values do not stop increasing above 2V/ns. Unfortunately,
the JEDEC spec
stops at 2V/ns. You can calculate the derating values above 2V/ns by using
the formulas
below. These formulas only apply to derating above 1V/ns. Below 1V/ns
there is another
function involved. However, these formulas will address your question.
Fractional
results should be rounded up to next highest integer
Derating @AC175 = 175ps - 175mV/SR, where SR is Slew Rate
Derating @AC150 = 150ps - 150mV/SR
Derating @DC100 = 100ps - 100mV/SR
Brian Moran
Signaling Development Group
Client Platforms
Intel Corporation
-----Original Message-----
From: Moran, Brian P
Sent: Thursday, February 04, 2010 9:48 AM
To: 'sreekanth soman'; Hermann Ruckerbauer
Cc: si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: DDR3 Slew Rate derating.
Derating values can and should be interpolated between slew rate entries.
Otherwise,
use the next highest SR value, but this will result in some incremental
loss in
calculated margin.
Brian Moran
Signaling Development Group
Client Platforms
Intel Corporation
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of sreekanth soman
Sent: Thursday, February 04, 2010 9:27 AM
To: Hermann Ruckerbauer
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR3 Slew Rate derating.
Hi,
If the slew rate is above 2 say - 2.5 V/ns,is the derate still the value
at
2 V/ns or more than that
I have not found any information regarding this on the web.
I am not sure if the jedec derating values can be extrapolated.
On 28 January 2010 22:29, Hermann Ruckerbauer <
hermann.ruckerbauer@xxxxxxxxxxxxx> wrote:
> Hello,
> as for most parts of the datasheets this data is not adjusted by the
> individual DRAM manufacturers. This kind of number are discussed in
> JEDEC when fixing the Spec, and each company designs it's DRAM to hit
> this target.
> So it's not really that the numbers are defined by the Hardware, but the
> Hardware is designed to hit this numbers. This is true for most of the
> parameters in the Datasheed (e. g. Setup/Hold absolute values).
> Reason for this is, that DRAMs are a commodity product that need to be
> interchanged without thinking. If the DRAMs would have different timing
> definitions it would be a big problem to adjust a system to different
> DRAM vendors. This is something nobody wants to do, and therefore this
> numbers are usually not changed by any DRAM vendor.
> The DRAM vendors also don't want to be better than the spec, because no
> customer will pay for this, and it would cost additional design effort.
>
> Whether a DRAM vendor is doing characterization testing or defining this
> parameter as "guaranteed by design" is up to each DRAM vendor. It is
> definitly no parameter that is checked in a high volume production test.
>
> regards
>
> Hermann
>
> Visit us on Embedded World 2010, 2. - 4. March 2010 in Nuernberg
> Follow our presentation on Tuesday, March 2nd, 11:00 a.m.
> "Signal Integrity in embedded computer systems"
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Veilchenstrasse 1
> 94554 Moos
> Tel.: +49 (0)9938 / 902 083
> Mobile: +49 (0)176 / 787 787 77
> Fax: +49 (0)3212 / 121 9008
>
>
> schrieb Heyfitch:
> > Brian,
> > I tried "to de-embed" the threshold compensation from the total
derating
> > tables so that to compare the SDRAM receiver timing at Vref from
> different
> > vendors.
> > However, a quick look at datasheets vendor from at least 3 vendors
> showsed
> > that they simply reprint JESD79-3C derating tables. Hence, there is no
> way
> > to infer any vendor specific info from their datasheets. Which brings
me
> to
> > my question: do SDRAM vendors actually test their IOs for compliance
with
> > the jedec derating table? Is this ATE testing or just spice
simulations?
> > Thank you.
> > Vadim
> >
> >
> > On Mon, Jan 25, 2010 at 5:50 PM, Moran, Brian P
<brian.p.moran@xxxxxxxxx
> >wrote:
> >
> >
> >> Surita,
> >>
> >> Let me try to give you a quick tutorial on derating, which should
answer
> >> your question. Please follow up if I don't answer your question
fully.
> >>
> >> Derating consists of two components. There is the reciever derating
at
> >> Vref,
> >> which tends to be 0ps at 1V/ns and above, and then increases as slew
> rate
> >> slows.
> >> This accounts for the fact that the SDRAM reciever timing starts to
> degrade
> >> as
> >> slew rate drops below 1V/ns. It's a function of the reciever design,
and
> >> this
> >> derating at Vref curve is defined by the SDRAM vendors. It has not
> chnaged
> >> significantly since DDR2. The second component of derating is
threshold
> >> compensation.
> >> This only comes into play when you measure flight times to AC or DC
> >> thresholds.
> >> Measuring to the AC or DC thresholds tends to distort the flight time
> >> measurements.
> >> This type of derating is dependent on threshold level, which si why
you
> get
> >> different
> >> derating tables as speed bin increases. Its not the speed the
matetrs,
> but
> >> the AC
> >> abd DC thresholds. So what the JEDEC task group did was to apply a
fixed
> >> adjustment
> >> to the tSU and tHD specs at Vref, to account for this distortion at
AC
> and
> >> DC.
> >> This adjustment is based on an input slew rate of 1V/ns. So if your
tSU
> at
> >> Vref was
> >> 500 ps, and your AC threshold is 175 mV, the tSU at AC is 325 ps. ON
> the
> >> hold side,
> >> if your tHD was 500 ps at Vref, then tHD at DC is 400 ps. They have
> >> pre-biased
> >> the tSU by 175ps to compensate for the additioanl flight time caused
by
> >> measuring
> >> to AC175, vs Vref.
> >>
> >> One quick thought exercise is to note that the margin calculated at
Vref
> >> and that
> >> calculated at AC threshold, for the same linear non-ledging signal
> should
> >> be equal.
> >> This goes back to when you had the option of measuring to Vref or to
> AC/DC.
> >>
> >> Ok, since they pre-biased the tSU spec by 175ps to account for AC
> threshold
> >> distortion
> >> in your flight time, what happens if your slew rate was actually
2V/ns.
> >> That means they
> >> pre-biased too much and have to take some back. This is where the
+88ps
> >> comes from. If
> >> the slew rate was 0.5V/ns then they did not compensate enough and you
> will
> >> get negative
> >> numbers in the threshold compensation table at SRs less than 1V/ns.
> >>
> >> The composite derating table shown in the JEDEC spec is the sum of
the
> >> reciever derating
> >> at Vref plus the threshold compensation. Threshold compensation is a
> purely
> >> algebraic
> >> formula, which is; 175ps - 175mV/SR for an AC threshold of 175mV. The
> final
> >> derating table
> >> is characterized by having 0 at 1V/ns, then increasingly positive
> numbers
> >> at SRs above 1V/ns
> >> and increasingly negative at SRs below 1V/ns. This trend is beginning
to
> >> break as we get to
> >> smaller and smaller AC thresholds, but for now it's a simpe rule of
> thumb.
> >>
> >> Also note that a positive number in the derating tbale always reduces
> >> margin, and visa versa.
> >>
> >> Like I said, follow up with another emial if its not clear. I
consider
> >> myself pretty
> >> knowledgable on derating and can provide some supporting docs if
needed.
> >>
> >>
> >> Brian Moran
> >> Signaling Development Group
> >> Client Platforms
> >> Intel Corporation
> >>
> >> -----Original Message-----
> >> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx
> ]
> >> On Behalf Of Surita Chandani
> >> Sent: Monday, January 25, 2010 2:15 PM
> >> To: si-list@xxxxxxxxxxxxx
> >> Subject: [SI-LIST] DDR3 Slew Rate derating.
> >>
> >>
> >>
> >>
> >> I am trying to understand DDR3 slew rate derating. Let
> >> us say we are working with a differential DQS with a fixed slew rate
of
> 2.0
> >> V/ns.
> >>
> >>
> >>
> >> When the DQ slew rate is 1.5 V/ns the setup time is 59
> >> ps. When the DQ slew rate increases to 2.0 V/ns, the setup time
> increases
> >> to 88
> >> ps. I thought the setup time would go down with a faster signal.
> >>
> >>
> >>
> >>
> >>
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--
sreekanth@ti
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