[SI-LIST] DDR3 Signal Quality & Timing Analysis - Probe Location at DRAM - Pin or Die?
- From: "Pugazharasan Selvanathan - ERS, HCL Tech" <pugazharasan.s@xxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 31 Oct 2011 15:43:10 +0530
Hello everyone,
My observations from the simulation results of a DDR3 interface (64 bit + 8 bit
ECC) with five Micron DRAMs:
In FAST corner, when CLK is probed at PIN of first DRAM in the daisy chain, it
has good signal quality (monotonic, no DC/Vref multi-crossing). But if it is
probed at DIE of the same DRAM, CLK is non-monotonic, multi-crosses DC and Vref
thresholds. Signal Quality improves at die of the other DRAMs as we progress
down the daisy chain, since the stub length between respective DRAMs and
termination decreases.
Give your thoughts to improve the signal quality at first DRAM's die.
Currently, the output impedance of DDR3 Controller is set to 40ohms, which is
the maximum O/P impedance it supports.
Thanks,
Pugazharasan Selvanathan
Member Technical Staff - Design Centric Services
HCL Technologies Ltd.
#94, South Phase, Ambatur Industrial Estate, Chennai-600058
Tel: +91-44-66892000 Extn: (2695)
www.hcl.com<http://www.hcl.com/>
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