[SI-LIST] DDR3 Fly by topology

From: "raja" <s.raja@xxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Tue, 7 Aug 2007 17:26:13 +0530

Hi Folks
         I am looking for some information related to the Fly-by topology used 
in the DDR3 Design. we are using onboard DDR3 memory devices interfaced with 
stratix III FPGA.  What should be the relation between the CK and DQS?
Regards
Raja
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[SI-LIST] DDR3 Fly by topology

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