[SI-LIST] Re: DDR3 - DQ lines in idle state
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: bbakshan@xxxxxxxxx
- Date: Thu, 18 Dec 2014 16:54:50 +0100
Hello,
if its pre-driven to 0.75 and then floating you will only see 0.75.
dependent on your system you will see this voltage fading away If you
have long times of no activity.
If there is no Write or Read on normal systems the DQ line should be
floating.
There can be some high ohmic resistors in the controller that would hold
the signal at midlevel,
but this is controller dependent..
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
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Am 18.12.2014 um 13:25 schrieb Boris Bakshan:
> Hi Hermann,
> Thank you for your quick reply.
> I probe the ODT pin and I see that it stays low when there is no Write
> activity and still, for some reason the voltage on the DQ lines is 0.75V.
> if ODT is cleared then this voltage can only be coming from the driver.
> Correct?
>
>
> On Thu, Dec 18, 2014 at 11:48 AM, Hermann Ruckerbauer <
> Hermann.Ruckerbauer@xxxxxxxxxxxxx> wrote:
>> Hello,
>>
>> Vref in no case, this is a very sensituve voltage.
>>
>> You might see VTT, but basically the Bus is floating if neither DRAM nor
>> Controller are driving.
>> Which level you see depends on the exact Timings the components use..
>>
>> Normally ODT should be enabled longer than the driver (independent of
>> read or write). in this case you should see a midlevel.
>> then ODT is switched off and the signal is floating. for long times of
>> inactivity you will see that the level is drifting (e.g . to GND).
>> But I have seen systems that e.g. switch off ODT to early and in this
>> case the Driver will drive to level to VDD or GND.
>> If now the Driver is switched off the signal will float at this level.
>>
>> Hermann
>>
>> EKH - EyeKnowHow
>> Hermann Ruckerbauer
>> www.EyeKnowHow.de
>> Hermann.Ruckerbauer@xxxxxxxxxxxxx
>> Itzlinger Strasse 21a
>> 94469 Deggendorf
>> Tel.: +49 (0)991 / 29 69 29 05
>> Mobile: +49 (0)176 / 787 787 77
>> Fax: +49 (0)3212 / 121 9008
>>
>> Am 18.12.2014 um 09:07 schrieb Boris Bakshan:
>>> Hello all,
>>> I'm now deep into study of DDR3 and more specifically covering the
>>> terminations in READ / WRITE cycles.
>>> I was wondering, what happens in IDLE state when no READ or WRITE
>> operation
>>> is activated? I see that either the controller or DRAM sets VREF voltage
>> on
>>> the DQ lines.
>>> Who's driving the line to VREF? is it the ODT of the DRAM or is it the
>>> controller?
>>>
>>> Many thanks,
>>> Boris.
>>>
>>>
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