[SI-LIST] Re: DDR3 Clock differential signal termination
- From: Tesla <emcesd@xxxxxxx>
- To: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- Date: Mon, 30 Jul 2012 14:54:27 +0800 (CST)
Brian Moran
Thank you very much for such detailed explaination.
After some documents search, i know the capacitor should be connected to VDD.
but a little new question, if it was connected to VDD, the clock switch noise
will run into VDD rail? or it already has clock switch noise(casued by data
signal line swing), so Add a little more more is OK
Thanks.
Tesla.
At 2012-07-26 06:16:47,"Moran, Brian P" <brian.p.moran@xxxxxxxxx> wrote:
>Tesla,
>
>There is some confusion regarding the origin and rational of the AC termination
>on DDR3 UDIMM and SODIMM Clock, but I can tell you that the dual Rtt
>termination
>is preferred over the single 100 ohm resistor in that it provides common mode
>termination.
>The clock can pick up common mode noise on the MB and without the common mode
>termination
>you will see a significant increase in the VIX range, where VIX refers to the
>crossing point.
>The DDR3 SDRAMs are sensitive to VIX. At least the spec implies this by
>forcing you to derate
>timing at VIX values outside of Vref +/-150 mV I believe. Now the second part
>of the question
>is why AC termination, as opposed to just connecting the center-tap to Vtt. I
>believe this
>was done in order to isolate the Vtt rail from Clock switching noise, which
>could have a
>harmful effect on CTL and CMD voltage margins. Note that the cap connects to
>Vdd.
>
>If I were doing a memory down point to point interface, as you descrbe, I
>would likely use
>a pair of Rtt reistors to Vtt and not worry about the AC cap. This cap has a
>negative
>impact in that it requires a certain amount of settling time coming out of
>sleep mode,
>which can trip you up. I don't think the additional swicthing noise on Vtt is
>a big issue,
>unless you are really pushing your topology and speeds.
>
>Brian Moran
>Signaling Development Group
>Client Platforms
>Intel Corporation
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>Behalf Of Hermann Ruckerbauer
>Sent: Wednesday, July 25, 2012 2:48 PM
>To: emcesd@xxxxxxx
>Cc: si-list
>Subject: [SI-LIST] Re: DDR3 Clock differential signal termination
>
>Hello,
>
>as far I remember there was a discussion in the Taskgroup about the
>crossing point of the clock signals. According to some simulations this
>was more stable when adding this capacitor.
>Nevertheless i have seen no system failing due to violation of Clock
>crossing point spec violation. Especially for small systems (usually
>with limited space) I recommend to skip this capacitor and just
>terminate differential.
>Somehow I though to remember that this capacitor was connected to VDD ?!?
>
>Best regards
>
>Hermann
>
>Our next Events:
>================
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>
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>Hermann Ruckerbauer
>www.EyeKnowHow.de
>Hermann.Ruckerbauer@xxxxxxxxxxxxx
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>schrieb Tesla:
>> Hi, Experts
>>
>> I am desing a DDR3 board using DDR3 chip. There is only one DDR3 chip on my
>> board. The clock signal is a differntial signal from my FPGA to DDR3 chip.
>> when i refer to other's schematic, i found two version for the termination
>> of clock signal:
>> 1 parallel a 100 ohm resistor in the DDR3 chip side
>> 2 parallel two series connected 50 ohm resistor in the DDR3 chip side, in
>> the connection point of the two resistor, a 0.1uF capacitor shunt to
>> ground(Like the terminatio for ethernet signal)
>>
>> Does the method 2 have special consideration? for EMC purpose or for the
>> thermal noise of resistor?
>>
>> Thanks
>>
>> Tesla
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>
>
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