[SI-LIST] Re: DDR3 Ccomp capacitance delay
- From: "Hany Fahmy" <hanymhfahmy@xxxxxxxxxxxxxxxxxxx>
- To: <Hermann.Ruckerbauer@xxxxxxxxxxxxx>, <petebenjamin730@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 18 Dec 2013 13:54:44 +0100
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Hi Pete, Agree with Hermann that best starting point is indeed the UDIMM,
SODIMM routing guidelines, below is an example of such routing rules. Also
agree w Feng that best shot is pre-layout analysis complemented with
post-layout analysis for fine-tuning. It depends on what is ur goal:
1N-1600, 2N-1600, 1N-1866, 2N-1866, pls. note that CNTL signals must run 1N
mode, while MA/CMD can be downgraded to 2N if needed, it depends on the
performance u r looking for:
CLK, CTRL, ADR/CMD Routing Guideines
General Guidelines
Segments TL0 & TL1 are routed at lower lead-in impedance (see geometry
worksheet)
Clocks are routed as differential pairs over the entire length
Clocks should be routed on stripline layers for as much of their length as
possible.
Clock far end termination structure shall be option A, as described on CLK
Termination tab.
Cterm should be located within 5 mm of the connector. Segment TL0A <= 5 mm
(200 mils)
Clocks, CTRL, and ADR/CMD signals are length/delay matched to the first
SDRAM (TL0 + TL1 + TL5) - See rules below.
Segment TL6 does not require length matching
Mirroring is not currently allowed on RC-B and RC-D, due to ranks being
split between top and bottom sides
CLK, CTRL & ADR/CMD Rtt resistors should be assigned to separate R-packs per
signal group
Topologies for RC-D, RC-E and RC-F vary from those shown here, but generic
rules apply.
Plane Referencing:
All CLK, CRTL and ADR/CMD signals are to be power referenced over the entire
length
Interconnect Type & Layer Assignments:
TL0 and TL5 segments are ustrip
TL1, TL2, TL3 and TL4 segments are stripline
TL6 segment can be ustrip or stripline
The CLK and CTRL signals for each rank should be routed on the same layers
Where reference plan transistions are required, place reference plane
stitching vias close to signal vias.
Length/Delay Matching:
CLK
Route CLK & CLK# of each clock pair as a differential pairs over the full
length.
Length match CLK & CLK# of each clock pair segment by segment to within 0.1
mm (4 mils)
Length match all CLKs segment by segment from connector to each SDRAM to
within +/- 0.25 mm (10mils).
Calculate velocity compensated stripline equivalent length for CLKs, from
connector to each SDRAM.
CTRL
Delay match (velocity compensated) all CTRL signals to CLK, from connector
to the first SDRAM load, to within +/- 1.0 mm (40 mils)
Delay match (velocity compensated) all CTRL signals to CLK, from connector
to the each subsequent SDRAM load, to within +/- 1.0 mm (40 mils)*
* Can accomplish this by length matching from via to via in loaded section,
if TL5 segments are the same length at each SDRAM.
Use delay matching worksheet to verify compliance at each SDRAM load.
ADR/CMD
Delay match (velocity compensated) all ADR/CMD signals to CLK, from
connector to the first SDRAM load, to within +/- 1.0 mm (40 mils)
Delay match (velocity compensated) all ADR/CMD signals to CLK, from
connector to the each subsequent SDRAM load, to within +/- 1.0 mm (40 mils)*
* Can accomplish this by length matching from via to via in loaded section,
if TL5 segments are the same length at each SDRAM.
Use delay matching worksheet to verify compliance at each SDRAM load.
TL5/TL9
The length of TL5 segment may vary from 0.5 mm (20 mils) to a maximum of 2.5
mm (100 mils) from net to net on CLK nets*
The length of TL5 segment may vary from 0.5 mm (20 mils) to a maximum of 6.3
mm (250 mils) from net to net on CTRL & ADR/CMD nets*
* On RC-E & RC-F topologies the TL9 segment is the equivalent of TL5 on
other cards.
Top and bottom side TL5/TL9 segments on 2 load per node topologies should be
matched to within +/- 0.25 mm (10 mils)
The length of all TL5/TL9 segments on a given net shall be matched to within
+/- 0.25 mm (10 mils) across all SDRAMs.
Note: All physical segment lengths are measured from center of pad to center
of pad.
Stub Lengths:
TL5 Length
Min
Max
CLK
0.5 mm
2.5 mm
CTRL
0.5 mm
6.5 mm
ADR/CMD
0.5 mm
TBD
Top vs Bottom Match: +/- 0.25 mm (10 mils)
Same Net Match: +/ - 0.25 mm (10 mils)
Velocity Compensation:
When performing delay matching the microstrip length should be converted to
equivalent stripline length via the following equation;
Equivalent Stripline Length = Microstrip Length / 1.1
Neck Down Length:
The neck down length is defined as the distance from the 1st SDRAM load that
the trace necks down to 4 mil width
The maximum neck down length for CLK, CTRL and ADR/CMD is 800 mils, unless
otherwise specified
Mirroring & Pin Swapping:
Mirroring should not be implemented when ranks are split across top and
bottom side
Mirroring is possible on RC-A, but is currently not recommended
Mirroring is possible on RC-E and F, but requires extensions to the SPD
module description
Hany Fahmy
CEO & Chief Consultant Officer
Intelligent Solutions BVBA
hanymhfahmy@xxxxxxxxxxxxxxxxxxx
http://www.intelligentsolutionsbvba.com/
http://www.linkedin.com/pub/hany-fahmy/66/852/b11
Phone: +32471650724
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Hermann Ruckerbauer
Sent: Tuesday, December 17, 2013 7:02 PM
To: petebenjamin730@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR3 Ccomp capacitance delay
Hello Pete,
The controllers that do not have the capability to adjust clock timings are
relying on the length matching. They send the clock centered in the CA eye
and expect that this timing relation is the same at the DRAM input.
BUT: I have seen several desings that have been matched to dead. They had a
perfect matching, but due to system boundary conditions this caused so much
trouble in the Layout that finally the desing had issues.
So when doing lengthmatching do it with some thinking .. 5mm mismatch causes
around 35ps decrease in your timing budget, but causes a lot of meanders. So
even it is techically easy possible to match to 100um physical length
sometimes it makes think much simpler to allow a bigger mismatch. But this
really depends on your system boundary conditions.
The input cap at the clock damps also your risetimes what reduces
reflections and helps for EMI.
From a timing point of view there are several aspects:
- The differential signal is faster than the single ended
- number of vias that might be different
- and it also depends on your configuration. On a two Rank system you have a
higher loading on the CA bus than on clock or on CTRL.
So overall this Lengthmatching is something where you can spend quite some
time in optimization. This is done already for the (JEDEC) DIMM's at a very
high level. Thats the reason why I recommend to take a look to the DIMM
designs even if you do solder down appliaction. If you do your own design
you should take care on all this differences. If you take a DIMM Layout as
starting point you know you have something working in the beginning ...
Herman
EKH - EyeKnowHow
Hermann Ruckerbauer
<http://www.EyeKnowHow.de> www.EyeKnowHow.de
<mailto:Hermann.Ruckerbauer@xxxxxxxxxxxxx>
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
Tel.: +49 (0)991 / 29 69 29 05
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
schrieb Pete Benjamin:
> Hi Experts,
>
> SODIMM and controller specifications I read all say to match (in time)
address/command nets to clock at DIMM input then at each dram input. It is
also recommended to add a 2.2pF to smooth the clock net but this cap delays
the clock net by around 50ps at first dram in the chain.
> Can someone explain why do a perfect length matching when clock is then
shifted? that reduces margin for address timing. Am I missing something
here?
> Some controllers don't even have capabilities to adjust clock timings.
>
> Thanks,
> Pete
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