[SI-LIST] Re: DDR3 16bit interfaces
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: bbakshan@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sun, 21 Dec 2014 15:57:17 +0100
Hello,
normally the controller and the DRAM will treat this as two independent
Byte lanes.
For writes and reads DQS to CLK timing realation need to be fulfilled.
For reads the DRAM gets one clock and needs to drive out the Data
accordingly
For write the routing length between the upper and lower byte might be
different wich will be covered by WriteLeveling (and read training) by
the controller
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
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Am 20.12.2014 um 19:20 schrieb Boris Bakshan:
> Hello all,
> I would like to ask your help with the following:
> With 16bit DRAM interfaces we have both UDQS and LDQS.
> In a write cycle, does a DDR controller write the two 8bit sets
> simultaneously?
> Should there be a shift between UDQS and LDQS? What is the the timing
> relationship between the two?
>
> Many thanks,
> Boris.
>
>
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