Hi Keeyoug,
I think your perception about DDR2 ODT is not correct. I am giving 2DIMM
slot case as an example. The slot which is being written will have
infinite ODT, while other slots will be terminated (example 60ohm) to
minimise reflection...
config write to slot1 (rank1/rank2) slot2 (rank1/rank2)
2R/2R slot1 infinite/infinite 60ohm / infinite
slot2 60ohm/infinite infinite/infinite
in DDR3 dynamic ODT, the value of ODT will be Rtt_WR (active DIMM) &
Rtt_nom (non-active DIMM) for WRITE operation. it will keep switching
between Rtt_WR to Rtt_nom based on Write/read operation without the need of
issuing MRS command. There are plenty of Micron app notes available to
explain about dynamic ODT operation. Multi-DIMM/multi-rank scenario in
DDR3 also needs careful understanding about ODT
Thanks
Sanjeev Gupta
www.sigintegrity-solutions.com
On Fri, Jul 1, 2016 at 7:16 AM, ê¶ê¸°ì <keeyoung.kwon@xxxxxxxxxxxxxx> wrote:
Hi Wang,
In addition to the difference between DDR2 and DDR3 regarding topologies
and loading conditions for ADD/CMD/Ctrl, ODT also has a difference.
For DDR2 4 DIMMs case, DQs use static ODT in a channel composed of 2
DIMMs. in this case, whenever you enables ODT in a channel, a DQ in 2 DIMMs
has a same ODT value.
Even though it can help reflection noise to be improved, it can cause
small voltage swing for DC condition. There is a trade-off.
Unlike DDR2, DDR3 supports dynamic ODT to provide more voltage margins
while improving reflection noise. In this case, when you write data at a DQ
Rx buffer in a DIMM, the other DQ Rx buffer can have different ODT value to
increase voltage level. For user applications, some memory vendors provide
ODT table based on the combination of RANK/DIMM.
As Sanjeev said, SI simulation will be helpful to analyze the margin.
Best Regards,
Keeyoung
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Sanjeev Gupta
Sent: Friday, July 1, 2016 1:39 AM
To: xiaoguang.wang@xxxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR2/DDR3 module issue help
Hi Wang
You can very well reproduce such scenario in simulation and root-cause
issue with proper models. DDR3 four-DIMM design working without any issue
does not imply that DDR2 design will also work. you need to properly
investigate the issue with your topology. DDR2 has different routing
topology (star) compared to DDR3 (daisy-chain). amount of loading is much
higher in DDR2.
Thanks
Sanjeev Gupta
www.sigintegrity-solutions.com
On Wed, Jun 29, 2016 at 2:04 PM, Wang Xiaoguang <
xiaoguang.wang@xxxxxxxxxxxxxx> wrote:
Hi all expert,
I am doing the application test for ddr3 and ddr2 UDIMM module, but
some problem makes things confused:(two platform : INTEL, AMD, both
have 4 module slot ) For ddr2, it always hang up if 4 modules are
pluged in together ,however it can work if one of 4 modules is removed
from the MB (3 modules works), And what's strange is that such fail
can't be improved by change of frequency, VDD, Temperature...
But for DDR3, there is no such problems.
From my side, I think ,
maybe the odt resistance of ddr2 is not ok that makes signal weak at
DRAM interface when work for the full load(4 modues together), and for
ddr3, it can work because there is calibration for ODT, which can help
to adjust the signal quality.
But not sure about the rootcause,
It there some comments/explanation/advise from your experience?
Wait for reply.
Best Regards
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