[SI-LIST] Re: DDR2 to Virtex 5 heating up and a few other questions

  • From: Hany Fahmy <hfahmy@xxxxxxxxxx>
  • To: "'fdunlap@xxxxxxxxxxxxxxxxx'" <fdunlap@xxxxxxxxxxxxxxxxx>, "'chuckiesanchez@xxxxxxxxx'" <chuckiesanchez@xxxxxxxxx>, "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
  • Date: Sun, 31 Jan 2010 16:55:36 -0800

To add for below: output drive strength should be programable on sdram side and 
also on Virtex side, do u have drive strength Ron control on Virtex side?
On sdram side, u can even choose half drive strength which meant to be used for 
low-power operation. 

Hany Fahmy

----- Original Message -----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx>
To: charlene radtke <chuckiesanchez@xxxxxxxxx>; si-list@xxxxxxxxxxxxx 
<si-list@xxxxxxxxxxxxx>
Sent: Sun Jan 31 12:44:07 2010
Subject: [SI-LIST] Re: DDR2 to Virtex 5 heating up and a few other questions

Hi Charlene,

If outputs are driving into terminated lines, which I presume they are, then 
more power will be dissipated in the output driver if the drivers are 
configured as class-II drivers versus class-I drivers. The "class" has to do 
with the drive strength. Furthermore, the series resistors that you used in 
your first design would limit output current, leading to reduced power 
dissipation. 

Both of these factors - use of class-II drivers and removal of series resistors 
- would lead to higher power dissipation in the second design.

Regards,

Frank

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of charlene radtke
Sent: Sunday, January 31, 2010 8:08 AM
To: si-list@xxxxxxxxxxxxx
Cc: chuckiesanchez@xxxxxxxxx
Subject: [SI-LIST] DDR2 to Virtex 5 heating up and a few other questions

Hello Experts,
I have a Virtex 5 FPGA connected to a Micron DDR2 device running at 180MHz. I 
designed a prototype and am now spinning the design for another phase of my 
program. Both designs use the same V5 and the only difference between the DDR2s 
used in each design is that one if a -3 and the other is a -3E version. 


These are the differences in the 2 design:
    The Layout had some improper return paths set up for Vref and Vtt that were 
corrected in the 2nd design. 
    I had series resistors on all data lines in the prototype that were removed 
in the 2nd design.
    I used all STTL18 class 1 on all IO in prototype. In the 2nd design I 
experimented with STTL18 class 1 and class 2 on control and data lines. (I read 
several app notes that mentioned both - and am currently confused on what is 
the correct approach)
    On both designs, data transfer stops working beyond 180MHz. 
    On the prototype design, I didn't notice the heat that I am noticing on the 
2nd design. 

    During my DDR2 tests, current consumption spikes up to 2.12A from approx 
1.2A as read from the power supplies.
    I am using a TI switch regulator to produce 1.8V.
    I am using a 0.9v LDO for VTT VREF that is enabled by a seperate FPGA on 
the board (not the V5).
    
According to the system monitor in the V5, the temperature peaks at about 66 
deg C on the 2nd design (about 10 deg hotter than the prototype design). I'm 
not sure if this is an issue with the DDR2 or the V5 but I really want to 
understand what could be causing this. I have checked bus contention and have 
also tried running DDR2 with various IO standards. 

Any brainstorming assistance and advice is appreciated.
Charlene


      
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