[SI-LIST] DDR2 problem
- From: Bryan Ackerly <bryan@xxxxxxxxxxxxxx>
- To: Si List <si-list@xxxxxxxxxxxxx>
- Date: Sat, 1 Nov 2014 11:13:52 +1100
Having some issues with a 225MHz DDR2 implementation at high temperature.
I am wondering if the problem might be power plane related. Doing a S21
analysis shows there is a bit of an impedance hole around 260MHz. Its magnitude
or frequency doesn't change with temperature, but unsurprisingly does with
applied voltage (1.8V). It's Q is not particularly high.
The issue showed up when we were forced to start using a die shrunk part. (Yes,
I know. That probably gives some clues). The original part worked over 100
degreesC with no problem at 225MHz. The new part starts failing at 60C. It
doesn't appear to be a refresh problem. The new part is supposed to work to
500MHz. But the interesting thing is that if the clock rate is dropped to
200MHz everything works fine. We did have some issues with the original
implementation at 250MHz at any temperature, hence why we were operating at
225MHz.
The power plane is not much bigger than a postage stamp. And the ground planes
for it are 0.12mm away. All data, address and control lines are length matched.
There are 8 bypass caps, all 100n. There is only one SDRAM and a Freescale
processor. Interconnects are all on internal layers. Line lengths are about
20mm. There are no series termination resistors as the layout is rather compact.
Regards,
Bryan Ackerly.
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