[SI-LIST] DDR2 length matching address and clock
- From: Balamanikandan K <kbmanick@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 22 May 2013 12:08:16 +0530
Dear Experts,
This is regarding the trace length matching between DDR2 address and clock
signals.
*As per my understanding, **the CLK should be centered within** **address
eye to measure and match the trace length. i.e. signals should like as
shown in figure.*
**
*[image: Inline image 1]*
**
**
I am using Hyperlynx tool for simulation.
Address line is connected from a processor to only one DDR2 DRAM(Not DIMM).
I am using a separate PLL clock driver which drives the clock to only one
DRAM.
No transmission lines are used (direct connection between driver and
memory). Terminations are provided.
*Under direct connections and equal load ( only one DRAM) :*
*
*
If the length adjustment measurement is to be right, then there should not
be any time difference (skew) between the clock signal and address signal
when the signal rises at the output of the drivers.
We have probed signals at the die as well as the pin of the driver output.
But the simulation results show the time difference. Clock signal advances
by 200 ps when compared the address signal.
When the skew at the output of the drivers is equal to zero, then only it
makes sense in probing the signals at the receiver and we can adjust and
keep the clock in center of the address eye.
Why there is a shift? Is this something related to ibis model? How to
correct it?
*Please clarify the doubts. Please Suggest me good guidelines if the
procedure followed by me is wrong.*
--
Best Regards,
Balamanikandan.K
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