[SI-LIST] Re: DDR2 in hyperlynx - voltage swing level too high
- From: Allan Wang <allanvv@xxxxxxxxx>
- To: Chockalingam Selvaraj <chockalingam.s@xxxxxxx>
- Date: Tue, 8 Feb 2011 01:00:49 -0500
Nevermind, didn't see the "design file" dropdown.
Allan
On Tue, Feb 8, 2011 at 12:52 AM, Allan Wang <allanvv@xxxxxxxxx> wrote:
> OK, I can simulate with ODT fine with the IC IBIS model. Now I'm
> trying to simulate with Micron's mt18htf51272ay-667a1.ebd DIMM model.
> How can I specify to use the ODT model? Am I going to have to modify
> the IC model file to default to the ODT model?
>
> Thanks,
> Allan
>
> On Tue, Feb 8, 2011 at 12:43 AM, Chockalingam Selvaraj
> <chockalingam.s@xxxxxxx> wrote:
>> Hi Allan,
>>
>> Its better to use the ODT anyways, if the ibis supports.
>> You will not see much variations when simulating at 200MHz though.
>>
>> By the way, I think the termination to Vtt should be at the receiving end of
>> the channel
>>
>> Thanks and regards
>> Chockalingam.S (Ck)
>> ________________________________________
>> From: si-list-bounce@xxxxxxxxxxxxx [si-list-bounce@xxxxxxxxxxxxx] On Behalf
>> Of Allan Wang [allanvv@xxxxxxxxx]
>> Sent: Tuesday, February 08, 2011 6:45 AM
>> To: Beal, Weston
>> Cc: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: DDR2 in hyperlynx - voltage swing level too high
>>
>> Doh, I see now.
>>
>> Thanks. The max speed I'll be using is 200MHz which should make this
>> easier. It seems to behave just fine without the discrete resistor
>> too.
>>
>> Allan
>>
>> On Mon, Feb 7, 2011 at 7:18 PM, Beal, Weston <Weston_Beal@xxxxxxxxxx> wrote:
>>> Allan,
>>>
>>> The voltage values 0.65 and 1.15 are the switching thresholds in the
>>> receiver. The actual voltage needs to go beyond these logic thresholds
>>> for the circuit to work correctly. The simulation results look fine at
>>> this speed, but will not behave so nicely at the correct speed.
>>>
>>> I wonder if you really need the discrete resistor since the receiver
>>> (DRAM) has on-die termination.
>>>
>>> Regards,
>>> Weston
>>>
>>>
>>> -----Original Message-----
>>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>> On Behalf Of Allan Wang
>>> Sent: Monday, February 07, 2011 3:20 PM
>>> To: si-list@xxxxxxxxxxxxx
>>> Subject: [SI-LIST] DDR2 in hyperlynx - voltage swing level too high
>>>
>>> Sorry if this is a bit basic for this mailing list. I'm trying to
>>> simulate DDR2 terminations according to Altera's external memory
>>> interface handbook. I can't figure out why my voltage swing is so
>>> large:
>>>
>>> http://i.imgur.com/kCRSE.png
>>>
>>> I believe the swing should be 0.65 - 1.15V.
>>>
>>> Allan
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