[SI-LIST] Re: DDR2 design
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: ivorlist@xxxxxxxxxxx
- Date: Wed, 22 Feb 2006 20:41:45 -0500
ivor
Okay, I think your gut tells you that you have a potential problem. I
see several issues here:
1) 75 ohms is a bit high for single ended trace impedance. This will
have a large impact on overshoot/undershoot at the receivers, if the
termination is not well matched. It will also have a large impact on
crosstalk.
2) Signal quality concerns matter first. You haven't told us your
application, but from your sig, you appear to be designing control
system processors. Given the liability issues involved, you might want
to be sure that you don't overstress a part and cause it to fail.
Simulation is only ways to be sure. The trial-and-error method only
works if you are lucky enough to build with worst case fast process
devices. If you are unlucky, you will build your boards with parts that
"seem" to work, but are not representative of the worst case.
3) Even at DDR2 333, timing closure can be a pain, especially with an
FPGA. Not only do you have issues with signaling ISI, but you also have
problems with SSO noise from the FPGA, and crosstalk jitter in the channel.
Regards,
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Ivor Bowden wrote:
> Hi Steve,
>
> I really do appreciate your comments. I know I have not done my
> homework, this was just dropped in my lap. I'm just looking for general
> comments, I don't expect anyone to run free sims for me. Comments like,
> "seems reasonable" or "no way" or "star routing might be better", etc.
> is about all I hoped for. I apologize if my request came off rude.
>
> I am open to simulation quotes, I believe it a good idea, if I can get
> approval.
>
> Sincerely,
>
> Ivor
>
> on 2/22/2006 4:34 PM steve weir wrote:
>
>> Ivor, maybe. Nothing sounds terribly wrong, but that is really
>> inadequate. You need to simulate, or get someone else to simulate for
>> you. Then you can see if any adjustments are needed and make them. You
>> need to account for what the silicon is up to as well as the trace.
>>
>> With all due respect your question comes off a bit like: "Guys, I
>> haven't done my homework, would someone do it for me?" If someone is so
>> willing, great. I would be surprised to see that. I would also suspect
>> the answer.
>>
>> If you want detailed free help, your best chance is from your chip
>> suppliers. Maybe Altera will run the simulation for you.
>>
>> Steve.
>> At 03:22 PM 2/22/2006, Ivor Bowden wrote:
>>
>>> Hi SI Experts,
>>>
>>> I am reviewing a layout for an embedded DDR2 design using 4 Micron DDR2
>>> chips with an Altera Cyclone controller. The memory is set up to be 64
>>> bits wide, 16 bits per chip.
>>>
>>> The target rate is 167MHz. The design is not simulated.
>>>
>>> Termination is as follows:
>>> ODT may be supported, still investigating.
>>> There is no series term.
>>> There is 0.9V stub term for control lines.
>>> There is a differential 100 ohm term for each clock pair (4 total).
>>>
>>> Routing is as follows:
>>> Control lines are daisy chained and length matched between the first
>>> DRAM and controller (about 1"), each DRAM (about .75") and the last DRAM
>>> and terminators (about .25"); total net length is about 3.5".
>>> Data lines are length matched at about 3" (controller to DRAM).
>>> Clock lines are length matched at about 4" (controller to DRAM).
>>> Trace impedance is targeted at 100 ohms for clock and control lines, and
>>> 75 ohms for data lines.
>>>
>>> Is this design likely to work? If not, what changes should be considered?
>>>
>>> I very much appreciate all comments. Thank you!
>>>
>>> Ivor Bowden
>>> Engineer
>>> Curtiss-Wright Controls
>>>
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