[SI-LIST] Re: DDR2 design
- From: "Grasso, Charles" <Charles.Grasso@xxxxxxxxxxxx>
- To: <ivorlist@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 23 Feb 2006 14:39:45 -0700
Hi Ivor,
To get immediate answers why not try contacting the support folks at the
FBGA company (Altera) and the memory (Micron) for any design guidelines
that they might have.? That way you can quickly see if you have any
"first-cut" issues. That should buy you the time you need to "fine-hone"
the design with simulations.
Best Regards
Charles Grasso
Senior Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Pager/Short Message: 3032042974@xxxxxxxx
Email: charles.grasso@xxxxxxxxxxxx;
Email Alternate: chasgrasso@xxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Ivor Bowden
Sent: Wednesday, February 22, 2006 4:22 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR2 design
Hi SI Experts,
I am reviewing a layout for an embedded DDR2 design using 4 Micron DDR2=20
chips with an Altera Cyclone controller. The memory is set up to be 64=20
bits wide, 16 bits per chip.
The target rate is 167MHz. The design is not simulated.
Termination is as follows:
ODT may be supported, still investigating.
There is no series term.
There is 0.9V stub term for control lines.
There is a differential 100 ohm term for each clock pair (4 total).
Routing is as follows:
Control lines are daisy chained and length matched between the first=20
DRAM and controller (about 1"), each DRAM (about .75") and the last DRAM
and terminators (about .25"); total net length is about 3.5".
Data lines are length matched at about 3" (controller to DRAM).
Clock lines are length matched at about 4" (controller to DRAM).
Trace impedance is targeted at 100 ohms for clock and control lines, and
75 ohms for data lines.
Is this design likely to work? If not, what changes should be
considered?
I very much appreciate all comments. Thank you!
Ivor Bowden
Engineer
Curtiss-Wright Controls
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