Bob, Without seeing what your waveforms look like and understanding the associated lab setup and probe locations, here are our thoughts on on the issue. Remember, the switching levels become tighter for DDR2-667/800 than for DDR2-533(Vref +/- 250 vs vref +/-200, although some data sheets only show the as vref +200/-250). Also, the more agressive device setup/hold specifications are based upon the worst case of the nominal and tangential DC-Vref and Vref-AC slew rates for ADDCMD, CTRL, CK, DQ, DM, and DQS. According to specifications, the signals must swing between the appropriate Vih/Vil DC/AC switching levels and then use the appropriate derating. This provides a more accurate, but still conservative picture of the actual timing margins. In reality, receivers don't switch strictly based upon hard voltage levels, but rather upon a function of the voltage and accumulated charge at the receiver after crossing Vref. SiSoft has done extensive analysis on receviers from multiple semiconductor vendors (including DDR2 receivers) and found that by applying a charge model concept significant margin gains, typically on the order of hundreds of picoseconds (up to a nanoseconds in extreme cases) can be achieved over the current DDR2 derating methodology. This is one explanation of why poor looking CTRL signals still result in systems that exhibit stable operation. SiSoft and Micron presented a paper at DesignCon2005 on DDR2 667/800 Mbs. You can find a link to the paper and presentation at the following location: http://www.sisoft.com/papers.asp Also, we will be presenting a TechForum at Designcon East this fall. A link to our abstract is below. http://www.iec.org/events/2005/designcon_east/conference/tf-mp4.html Regards, Doug Douglas Burns Vice President, Consulting Services/Chief Consultant Signal Integrity Software, Inc. 6 Clock Tower Place Maynard, MA 01754 978-461-0449 x14 dburns@xxxxxxxxxx -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Bob McNamara Sent: Monday, June 06, 2005 1:50 PM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] DDR2 at speeds faster than DDR2-533 I bought a couple of "the ultimate game machine" DDR2 motherboards just to see how great they really were (not because I wanted to waste endless hours playing mindless video games). ;-) One motherboard uses the Intel chipset and the other uses the NVidia chipset. I decided to scope out some of the DDR2 signals to see how much margin they have at various speeds. I found that at DDR2-533, the signals look pretty good and (at least for my sample of one) appear to meet worst case timing margins. Most of the command/address signals use 2T timing (i.e., they use two clock ticks to become valid). A few of the signals (CS, ODT, CKE) must meet the more stringent 1T timing. So I looked at CS as an example of a worst case signal. At DDR2-667, the CS signal just doesn't hit the Vihac/Vilac thresholds when it's toggling high-low-high-low. But there is enough of a swing above and below Vref that you can see why the memory might actually work well enough for the computer to boot and even appear stable. At least for my one sample at room temperature and nominal voltage. Of course as the speed increases to DDR2-800, the CS signal only looks worse. In fact it's so bad that I wouldn't expect the system to pass a memory test or boot. But it *does* pass the memory test, boot, and appears to be stable. Has anyone else looked at this? Maybe I'm not supposed to "look under the hood" when I buy commodity performance hardware? Can anyone point me at a system that really does meet worst case timing at DDR2-800 and/or DDR2-667? We've all heard and/or seen examples of how sloppy and slipshod the engineering is for products in the PC space. So please don't waste bandwidth with a reply unless you have something more to contribute than "Yeah, it's really awful". Thanks, Bob ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu