[SI-LIST] Re: DDR2 VTT terminations
- From: "Ferhat Yaldiz" <ferhat.yaldiz@xxxxxxxxxxxxxx>
- To: "'Edi Fraiman'" <EdiFraiman@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 10 Jul 2008 16:50:36 +0300
Hi Edi,
I recommend first configuration (Like DIMM design). But, you must try to
simulate different alternatives.
Regards,
Ferhat YALDIZ
Hardware Design Eng.
TUBITAK - Information Tech. Inst.
TURKIYE
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Edi Fraiman
Sent: Thursday, July 10, 2008 4:41 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR2 VTT terminations
Hi all,
Currently I am designing board with Freescale CPU MPC8360 and DDR2.
There are four DDR2 chips that connected to CPU.
Address and control signals are common to all four DDR2 chips (one
address line feeds four DDR2 chips).
Address/control routed as BALANSED "T- SHAPE" and "T" branches are equal
to all address/control signals.
Now I have doubts about placement for VTT terminations for
address/control signals.
What the best configuration?
1. One VTT termination resistor in the middle of "T-SHAPE"
(between two branches)
2. VTT termination near each DDR2 chip at the end of the branch.
Best regards,
Edi Fraiman
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