Hi all, Currently I am designing board with Freescale CPU MPC8360 and DDR2. There are four DDR2 chips that connected to CPU. Address and control signals are common to all four DDR2 chips (one address line feeds four DDR2 chips). Address/control routed as BALANSED "T- SHAPE" and "T" branches are equal to all address/control signals. Now I have doubts about placement for VTT terminations for address/control signals. What the best configuration? 1. One VTT termination resistor in the middle of "T-SHAPE" (between two branches) 2. VTT termination near each DDR2 chip at the end of the branch. Best regards, Edi Fraiman ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu