[SI-LIST] DDR2 Trace Length Margin
- From: Gregory R Edlund <gedlund@xxxxxxxxxx>
- To: sreekanthn@xxxxxxxxxxxxxxx
- Date: Tue, 22 Jul 2008 08:13:57 -0500
Hello Sreekanth,
Brian gives a good overview of the timing requirements for DDR2 (DQ to
DQS, ADDR/CNTL to CLK, DQS to CLK). All this sits within a larger context
of timing margins, i.e. if your memory controller has a poor DQ-DQS
specification, you can tolerate less length variation between DQ and DQS
on the circuit board.
If you'd like to see an analysis of the big picture, I wrote a book that
has a chapter on DDR2 timing. It does not cover all the timing
constraints, but it gives you a sense for how other factors like crosstalk
affect your decisions on length matching. You can even check out the
electronic copy on Amazon to see if it's what you want. "Timing Analysis
and Simulation for Signal Integrity Engineers." If you're interested in
lab verification, there is a larger book that includes some of the timing
material called "A Signal Integrity Engineer's Companion."
Good luck.
Greg Edlund
Senior Engineer
Signal Integrity and Timing
3605 Hwy. 52 N Bldg 050-2
Rochester, MN 55901
gedlund@xxxxxxxxxx
Msg: #2 in digest
From: "sreekanthn" <sreekanthn@xxxxxxxxxxxxxxx>
Subject: [SI-LIST] DDR2 Trace Length Margin
Date: Mon, 21 Jul 2008 17:36:51 +0530
Hi Experts,
I would like to know the length matching requirement of a DDR2 design.
I have two memory devices in my board (NOT DIMMs).
Each has 16 bit data (Total 32) ,Each byte has its own Data strobe and
Mask
signals.
Datas ,Stobes,Masks,Clk etc are point to point topology.
Address and other common signals ( RAS,CAS,WE,RE,CS,CLKEN etc...) has to
be
routed in T topology.
Could someone please explain the rule of length matching for each groups.
Is there any standard docs available ? I refered JDEC specs, I could n't
get any routing recommendations.
How can we engineer the trace length margin ?
My Max clock would be 667MHz.
Regards,
Sreekanth
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