[SI-LIST] DDR2 SSTL class I interface

From: vijayan s <vicchemical@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Thu, 11 Feb 2010 12:31:43 +0530

Hi all,
In my design, I am using the x8 DDR2 memory interfaced with FPGA.

FPGA can only support SSTL Class I standard and interfaced with micron
memory ( mem datasheet not specified class I or II). When I saw the
electrical characteristics of Class I and Class II sstl, it shows no
difference except the Iol current. For class I, it is around 6mA and for
class II it is 13.4mA.

Here my question is,

1. Whether SSTL 1.8V Class I standard supports bidirectional signals,
because in some forum I saw it supports only unidirectional interface?
2. What design modification I have to take care when connecting ClassI to
ClassII IO standard ? On termination wise, Iam aware of providing one series
+ parallel  termination for class I and two pull up +one sreies termination
for class II. Except this termination, I have to take care on any other on
design ?

Please comment.

Regards,
Vijayan


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[SI-LIST] DDR2 SSTL class I interface

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