Hi everybody... I am novice in the signal integrity and I trying to perform signal integrity analysis of the DDR2 DIMM module only... What kind of simulation models I need to simulate electrical loading on the DDR2DIMM connector? On the one side is IBIS model of the DRAM, but what is it on the another side(connector)... JEDEC specification is for the Motherboard vendors, Memory modul EBD Simulation models also... Who defines level of the signals on the DIMM connector? Thanks for your help, Aleksandar Djokic Bluestar Serbia ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu