[SI-LIST] Re: DDR-1 termination (short point-to-point)

  • From: "Anders Frederiksen" <af@xxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Sun, 6 Feb 2005 03:12:16 +0100 (CET)

Hi All,

Thanks for your inputs so far!

> Kristiaan, SSN can be a challenge with big FPGA packages and large parallel
> busses.  It is important to plan the pin assignments so that the crosstalk
> / SSO does not blow the timing budget, or subject the chip I/O to excess
> voltage swing.  The Xilinx ISE tools do not provide SSO, or in-package PDS
> droop information.

However I think the Xilinx memory tool does actually take simultaneous switching
outputs into account.

> You are corect that V2P inputs really need to be held to 3V absolute, or
> device life will be shortened.

Argh! They're clamped, but not for "ordinary" overshoots?

> The devil with DCI is that it alters the
> timing and will limit the speed at which a V2P DDR interface can
> run.  Xilinx' reference designs call for DCI disabled with DDR on V2, and V2P.

Another "downer" with DCI is that it consumes power! Especially when one must
terminate to Vio/2...

>>how many bits if I might ask? 256? 512?

No, I'll only be at 112 or something in that area...

>> This number will probably get you in
>>trouble when using the SSTL2C2 on the V2P regarding the SSO number.
>>
>>If my poor memory serves me well, I think the V2P is quite sensitive to
>>over/undershoot on its IO. (Check the datasheet and with your FAE when in
>>doubt.)
>>I once simulated a design with 5 cm lines, resulting in (for the data-lines)
>>just resistors at the DDR (just like Ravinder) BUT with DCI on the V2P IO
>>pads (mind chip dissipation though)

Vio/2 parallel?

>>; guess this won't cut your problem
>>though.
>>
>>As Julia and others have stated, I also prefer proper termination on DDR
>>interfaces; it is what the original SSTL2 spec stands for.

Hmm - "proper termination" would not be my choice of words when not used for 
DIMMs:
Adding stubs seems silly ;-)
Proper termination as in parallel to Vtt in both ends is of course great. Guess 
I'll
end up with termination like this "mid-line" (just outside each of the
BGAs(DDR/V2P)) - or simulate... Not quite sure if I'll also requre the series
resistors at the DDR end also (?).

I any case I was just naively hoping for a little less... :-P
How about the _really_ short ones??? ;-)

Cheers,
 Anders


>>Kind Regards,
>>Kristiaan
>>
>>
>>-----Original Message-----
>>From: Julia Nekrylova [mailto:JNEKRYLO@xxxxxxxxxx]
>>Sent: 4-feb-05 21:34
>>To: kristiaan.depaepe@xxxxxxxxx; af@xxxxxx; si-list@xxxxxxxxxxxxx
>>Subject: RE: [SI-LIST] Re: DDR-1 termination (short point-to-point)
>>
>>A simple SI and timing simulation would not include SSN effects (ground
>>bounce, power noise) that in the presence of terminations are far more
>>manageable. This is just a reminder that SSN can kill DDR performance,
>>not just reflections and crosstalk.

Noted!

>>Regards,
>>Julia

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